Patent US7254718B2 successfully refreshed from Google Patents.
US7254718B2
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Tamper-resistant processing method
Assignee: Hitachi Ltd
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Filing: 2001-08-29
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Granted: 2007-08-07
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Expires: 2021-08-29
Abstract
Abstract The subject of the disclosed technology is, when a crypto-processing is performed utilizing an information processing device buried in an IC card, etc., to decrease the relationship between the waveform of the consumption current and the contents of the crypto-processing as a countermeasure against a tamper which observes the waveform of a consumption current. A solution means is shown in the following. When a decryption processing of an RSA cryptogram is performed according to CRT, in step 608, for every unit bit block of XP a modular exponentiation calculation is performed, and the partial result of CP up to the calculated bit block is stored in a memory. In step 609, for every unit bit block of XQ a modular exponentiation calculation is performed and the partial result of CQ up to the calculated bit block is stored in a memory. In step 606, a random number is generated, and in step 607, it is decided that step 608 is to be executed or step 609 is to be executed corresponding to the value of the random number.
Inventors
- 👤 Masahiro Kaminaga
- 👤 Takashi Endo
- 👤 Takashi Watanabe
- 👤 Masaru Ohki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:05
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/72; G06F7/723; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30181; H; H04; H04L; H04L9/00; H04L9/002; H04L9/003; H04L9/30; H04L9/3006; H04L9/302; G06F2207/00; G06F2207/72; G06F2207/7219; G06F2207/7223; G06F2207/7252; H04L2209/00; H04L2209/08; H04L2209/12; H04L2209/127
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
184 words
A tamper-resistant processing method comprising the steps of: (a) deciding whether to first transfer one operation unit in the bit pattern of data A in a memory to a first register R 1 and then to transfer one operation unit in the bit pattern of data B in the memory to a second register R 2 , or to first transfer one operation unit in the bit pattern of said data B to said second register R 2 and then to transfer one operation unit in the bit pattern in said data A to said first register R 1 ; (b) transferring each operation unit to said registers R 1 and R 2 , respectively, in accordance with the order of transfer decided in step (a); (c) executing a predetermined arithmetic operation on the contents of said first register R 1 and the contents of said second register R 2 ; (d) storing the result of said arithmetic operation in the memory, (e) repeating the steps from (a) through (d) until said arithmetic operation for said data A and said data B is finished.
Claim 2
Dependent Claim
184 words
A tamper-resistant processing method comprising the steps of: (a) deciding whether to first transfer one operation unit in the bit pattern of data A in a memory to a first register R 1 and then to transfer one operation unit in the bit pattern of data B in the memory to a second register R 2 , or to first transfer one operation unit in the bit pattern of said data B to said second register R 2 and then to transfer one operation unit in the bit pattern in said data A to said first register R 1 ; (b) transferring each operation unit to said registers R 1 and R 2 , respectively, in accordance with the order of transfer decided in step (a); (c) executing a predetermined arithmetic operation on the contents of said first register R 1 and the contents of said second register R 2 ; (d) storing the result of said arithmetic operation in the memory, (e) repeating the steps from (a) through (d) until said arithmetic operation for said data A and said data B is finished.
Claim 3
Dependent Claim
171 words
A tamper-resistant processing method comprising the steps of: (a) deciding whether to first transfer one operation unit of data A in a memory to a first register R 1 and then to transfer one operation unit of data B in the memory to a second register R 2 , or to first transfer said one operation unit of the data A to said second register R 2 and then to transfer said one operation unit of the data B to said first register R 1 ; (b) transferring each operation unit to said registers R 1 and R 2 , respectively, in accordance with the order of transfer decided in step (a); (c) executing a predetermined arithmetic operation on the contents of said first register R 1 and on the contents of said second register R 2 ; (d) storing the result of said arithmetic operation in the memory; (e) repeating the steps from (a) through (d) until said arithmetic operation on said data A and said data B is finished.
Claim 4
Dependent Claim
171 words
A tamper-resistant processing method comprising the steps of: (a) deciding whether to first transfer one operation unit of data A in a memory to a first register R 1 and then to transfer one operation unit of data B in the memory to a second register R 2 , or to first transfer said one operation unit of the data A to said second register R 2 and then to transfer said one operation unit of the data B to said first register R 1 ; (b) transferring each operation unit to said registers R 1 and R 2 , respectively, in accordance with the order of transfer decided in step (a); (c) executing a predetermined arithmetic operation on the contents of said first register R 1 and on the contents of said second register R 2 ; (d) storing the result of said arithmetic operation in the memory; (e) repeating the steps from (a) through (d) until said arithmetic operation on said data A and said data B is finished.
Claim 5
Dependent Claim
42 words
A tamper-resistant processing method of claim 2 wherein whether to first transfer one operation unit of the data A to said first register R 1 or to said second register R 2 is determined with the use of a generated random number.
Claim 6
Dependent Claim
19 words
A tamper-resistant processing method of claim 2 wherein said predetermined arithmetic operation is the operation for an arithmetic sum.
Claim 7
Dependent Claim
19 words
A tamper-resistant processing method of claim 2 wherein said predetermined arithmetic operation is the operation for an arithmetic product.
Claim 8
Dependent Claim
28 words
A tamper-resistant processing method of claim 2 wherein said predetermined arithmetic operation is any one of the logical sum OR, logical product AND, and exclusive logical sum EXOR.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-08-06 | 2011-02-05 | 2011-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-08-06 | 2015-02-05 | 2015-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-08-06 | 2019-02-05 | 2019-08-07 | $7700.00 | Window Closed / Lapsed |