Secure execution of program instructions provided by network interactions with processor

Claim 2

A particularly configurable processor for processing computer programs which are selectively operable on said particularly configurable processor, comprising: a memory defining a storage location for a key; an instruction decoder programmably configured for decoding encrypted instruction op codes when supplied with key information from said memory, without decrypting the encrypted op codes into standard op codes; and circuitry for terminating decoding in the absence of timely receipt of additional key information.

Claim 3

The processor of claim 1 , wherein the logic circuitry is reconfigurable, said reconfigurable logic circuitry calculating the results of execution of an instruction.

Claim 4

The processor of claim 2 , wherein the logic circuitry calculates the results of the execution of an instruction including provisions for accepting correct data operands and plausible wrong data operands.

Claim 5

The processor of claim 2 , wherein: the key is stored in more than one memory cell type including a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (E 2 PROM), and a Random Access Memory (RAM); and a serial number in ROM which participates in allocation of logic gates and routing of signals, and communicated to the compiler to inform the compiler of custom allocation and routing.

Claim 6

The processor of claim 1 , wherein an output register for data results is able to contain both correct results and plausible wrong results, the results in word locations in the output register coordinated by the key.

Claim 7

The processor of claim 1 , further comprising: program instruction op codes provided in a pipeline architecture; and an information key established as instruction security commands at a plurality of steps in said pipeline architecture, wherein an arithmetic logic unit (ALU) provides variability of logic circuitry for execution of encrypted op codes or standard op codes that provide standard instruction operation types.

Claim 8

The processor of claim 1 , wherein: the key includes bits optionally expanded into a larger set of bits which control the instruction decoder, signal routing, and logic gate reconfiguration; and the key provides a capability of controlling signal routing, and logic gate reconfiguration.

Claim 9

The processor of claim 7 , further comprising an output register for data results able to contain both correct results and plausible wrong results which are in word locations in the output register coordinated by the key.

Claim 10

The processor of claim 8 , further comprising: a plurality of reconfigurable logic gates able to calculate results of execution of an instruction; said plurality of the logic gates including provisions for accepting correct data operands and plausible wrong data operands; and said plurality of the logic gates including provisions for outputting correct results along with plausible wrong results.

Claim 11

The processor of claim 9 , wherein: a plurality of the memories are dispersed within a layout; a plurality of reconfigurable logic gates able to calculate results of execution of an instruction; said plurality of the logic gates including provisions for accepting correct data operands and plausible wrong data operands; and said plurality of the logic gates including provisions for outputting correct results along with plausible wrong results.

Claim 12

The processor of claim 1 , further comprising: the key providing a capability of re-allocating memory resources and register resources; a serial number in ROM which participates in allocation of logic gates and routing of signals; and the serial number used in combination with the key in providing said capability.

Claim 13

The processor of claim 1 , wherein variations of data numeric representations are coordinated by the key and the encrypted instruction op codes.

Claim 14

The processor of claim 1 , wherein an instruction buffer contains logic which can route a subset of the instruction bits from bit location in the buffer to destination logic circuitry which reach a programmable instruction decoder and an instruction buffer interdependency checking logic block.

Claim 15

The processor of claim 1 , further comprising: logic circuitry configured to process data coded in various numeric representations and the logic circuitry able to accept results of the instruction execution using various numeric representations; logic circuitry configured to immediately process said coded data; and the data representation able to change several times during the execution of a program so that numeric encodings of input data operands and output data results can vary.

Claim 16

The processor of claim 1 , further comprising: program instruction op codes provided in a pipeline architecture; and information keys established as instruction security commands at a plurality of steps in said pipeline architecture, wherein an arithmetic logic unit (ALU) provides variability of logic circuitry for execution of encrypted op codes or standard op codes that provide standard instruction operation types.

Claim 17

The processor of claim 1 , wherein the logic circuitry is reconfigurable and including provisions for outputting correct results along with plausible wrong results.

Claim 18

The processor of claim 1 , wherein data and instructions are provided to a computer via program information includes an intentional introduction of errors which are correctable with error correction algorithms, said correction algorithms pre-selected according to the key.

Claim 19

The processor of claim 17 , further comprising: an instruction buffer which contains logic which can route a subset of the instruction bits from bit location in the buffer to destination logic gates which reach a programmable instruction decoder and an instruction buffer interdependency checking logic block; and said correction algorithms pre-selected according to long instruction words and changed on a periodic basis by codes provided in the instructions gathered into the instruction buffer.

Claim 20

The processor of claim 18 , wherein instruction buffer interdependency checking logic includes any combination of the following: multiplexers to select a subset of bits from each long instruction word in the instruction buffer to be logically combined to match a sequencer value; a sequencer incremented at times determined by the key and which is reset upon the occurrence of the sequencer reset code in the instruction buffer; distribution of bits for one encrypted op code across several long instruction words in the instruction buffer; distribution of several encrypted op codes around the long instruction words in the instruction buffer; a program counter which does not normally increment by one, but which increments by some other constant or variable amount determined by a serial number, the key, and the sequencer value so that encrypted op codes which will be used sequentially in time do not occur sequentially in the instruction buffer, and for which, the time sequential chosen op codes are selected by the multiplexer controlled by the key, the serial number, and the sequencer; error correction circuits controlled by the key, sequencer, and supplementary error correcting codes received from the instruction buffer by means of the multiplexers; and dependency validation codes received through the multiplexer of the instruction buffer checked by logic circuits that depend on the key, the serial number, instruction bits, and camouflage bits.

Claim 21

The processor of claim 17 , wherein dependency validation codes received through the multiplexer of the instruction buffer are checked by logic circuits that depend on the key, a serial number, instruction bits, and camouflage bits so that incorrect validation bits provide an alarm.

Claim 22

The processor of claim 20 , wherein upon receipt of said alarm, interdependency checking logic writes an audit code and is capable of terminating program execution.

Claim 23

The processor of claim 1 , further comprising: a plurality of storage locations for keys, with the keys further determining storage locations of satellite keys and satellite access flags, said locations intentionally varied; key-dependent storage of remote access approval flags, the remote access approval flags encoded so as to obscure the locations of said approval flags; the instruction decoder programmably configured for using a null key for a default unencrypted instruction set; and the instruction decoder programmably configured for selecting from any of several stored keys so that several independent encrypted and unencrypted programs may be executed sequentially by installing each different key when needed, which also reallocates memory and register resources that are securely partitioned from each other.

Claim 24

Method for processing computer programs selectively operable on one or more selected individual processors, comprising: programming an instruction decoder to decode encrypted instruction op codes, without decrypting them into standard op codes; using logic circuitry for requiring network handshaking; and providing additional key information through the network handshaking, said additional key information required for continued operation.

Claim 25

Method for processing computer programs selectively operable on one or more selected individual processors, comprising: programming an instruction decoder to decode encrypted instruction op codes, without decrypting them into standard op codes; using logic circuitry for requiring network handshaking; and providing additional key information through the network handshaking, said additional key information required for continued operation.

Claim 26

The method of claim 23 , further comprising: using the reconfigurable logic gates for calculating the results of execution of an instruction; the calculation of results of the execution of an instruction including accepting correct data operands and plausible wrong data operands; and outputting correct results along with plausible wrong results.

Claim 27

The method of claim 24 , further comprising: using at least a portion of the reconfigurable logic gates for calculating the results of the execution of an instruction; using said portion of the logic gates for accepting correct data operands and plausible wrong data operands; and using said portion of the logic gates for outputting correct results along with plausible wrong results.

Claim 28

The method of claim 24 , further comprising: providing a key shared with a compiler; encrypting standard instruction op codes with the compiler using the key; and expanding key bits in the key into a larger set of bits which control the instruction decoder, signal routing, and logic gate reconfiguration.

Claim 29

The method of claim 23 , further comprising: providing program instructions in a pipeline architecture; and establishing information keys as instruction security commands at a plurality of steps in said pipeline architecture, wherein an arithmetic logic unit (ALU) provides variability of logic gates for execution of encrypted op codes or standard op codes that provide standard instruction operation types.

Claim 30

The method of claim 23 , further comprising using the logic circuitry for requiring network handshaking on a periodic basis.

Claim 31

The method of claim 23 , further comprising using the logic circuitry for requiring network handshaking periodically based on time of a previous network handshaking procedure.

Claim 32

The method of claim 23 , further comprising: providing a key shared with a compiler, the key used by the compiler to encrypt standard instruction op codes into encrypted instruction op codes; and using the key to coordinate the variations of the data numeric representations and the encrypted instruction op codes.

Claim 33

The method of claim 30 , further comprising using the key to provide a capability of re-allocating memory resources and register resources.

Claim 34

The method of claim 23 , further comprising routing a subset of the instruction bits through an instruction buffer to destination logic gates, which reach a programmable instruction decoder and an instruction interdependency checking logic block.

Claim 35

The method of claim 23 , further comprising providing a choice of using encrypted instruction op codes or standard instruction op codes.

Claim 36

The method of claim 23 , further comprising: providing a key shared with a compiler; encrypting standard instruction op codes with the compiler using the key; and providing data and instructions to a computer via program information including an intentional introduction of errors correctable with error correction algorithms, said correction algorithms pre-selected according to the key.

Claim 37

The method of claim 23 , further comprising: providing a key shared with a compiler; encrypting standard instruction op codes with the compiler using the key; providing data and instructions to the computer via program information includes an intentional introduction of errors which are correctable with error correction algorithms, said correction algorithms pre-selected according to the key and long instruction words; and changing the correction algorithms on a periodic basis by codes hidden in the instructions gathered into an instruction buffer.

Claim 38

The method of claim 23 , further comprising: providing dependency validation codes buffer checked by logic circuits that depend on a key; and in the case of incorrect validation bits, providing an alarm.

Claim 39

The method of claim 33 , further comprising writing an audit code in response to said alarm and terminating program execution.

Claim 40

The method of claim 23 , further comprising: using logic for requiring network handshaking; and further using the network handshaking to provide additional key information for continued operation.

Claim 41

Method for compiling computer programs for operability on selected ones of individual processors, comprising: providing encrypted instruction op codes for execution by an instruction decoder to decode without decrypting into standard op codes; and providing additional key information through network handshaking, said additional key information required for continued operation.

Claim 42

Method for compiling computer programs for operability on selected ones of individual processors, comprising: providing encrypted instruction op codes for execution by an instruction decoder to decode without decrypting into standard op codes; and providing additional key information through network handshaking, said additional key information required for continued operation.

Claim 43

The method of claim 39 , further comprising: providing a key shared with a compiler; and encrypting standard instruction op codes with the compiler using the key.

Claim 44

The method of claim 40 , further comprising using a serial number in combination with the key.

Claim 45

The method of claim 39 , further comprising: providing dependency validation codes; and in the case of incorrect validation bits, providing an alarm.

Claim 46

A particularly configurable processor for processing computer programs which are selectively operable on said particularly configurable processor, characterized by: variable logic circuitry able to execute encrypted op codes; and logic for requiring network handshaking, the network handshaking further used to enable continued operation.

Claim 47

A particularly configurable processor for processing computer programs which are selectively operable on said particularly configurable processor, characterized by: variable logic circuitry able to execute encrypted op codes; and logic for requiring network handshaking, the network handshaking further used to enable continued operation.