Patent US3708886A successfully refreshed from Google Patents.
US7245668B2
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US
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Clock modulation systems
Assignee: Individual
•
Filing: 2005-12-10
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Granted: 2007-07-17
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Expires: 2025-12-10
Abstract
Abstract Shaped Clocked (SC) and Clock Modulation (CM) systems, signal generation-reception, processing and CM implementations. Systems having a first and second shaped clock signal and providing shaped clocks to a selector switch and to a signal transmitter. The selectable clock signal parameters include symmetrical and non-symmetrical shaped clock signals, shaped filtered continuous clock signal patterns, shaped encoded clock signals, variable rise and fall time clock signals, clock signals having shaped adjustable on and off duration, multilevel and shaped clock signals and asynchronous clock signal information transmission means. The Clock Modulation (CM), Shaped Clocked (SC) systems, also designated as Feher Keying (FK) systems or FK processors are also used in conjunction with cross-correlated quadrature and also non quadrature modem systems as input drive signals to FM VCO based systems, to SSB to VSB to DSB-SC to QAM, and/or to coded systems.
Inventors
- 👤 Kamilo Feher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:21
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4902; H04L27/00; H04L27/0004; H04L27/18; H04L27/32; H04L27/34; H04L7/00; H04L7/0008; H04B; H04B2201/00; H04B2201/69; H04B2201/707; H04B2201/70703; H04L27/26; H04L27/2601; H04L27/2626; H04L27/2627; H04L27/2637
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
75 words
A dock modulation system comprising: a clock modulator generating Bit Rate Agile (BRA) clock shaped, clock modulated signals; a modulator filter band limiting the said modulated signals; a signal transmitter transmitting the clock modulated bandlimited signals; a receiver and demodulator for reception and demodulation of clock modulated signals; and a Bit Rate Agile (BRA) demodulator filter for filtering the received signals said demodulator filter having intentionally miss-matched filter parameters to that of the modulator filter.
Claim 2
Dependent Claim
75 words
A dock modulation system comprising: a clock modulator generating Bit Rate Agile (BRA) clock shaped, clock modulated signals; a modulator filter band limiting the said modulated signals; a signal transmitter transmitting the clock modulated bandlimited signals; a receiver and demodulator for reception and demodulation of clock modulated signals; and a Bit Rate Agile (BRA) demodulator filter for filtering the received signals said demodulator filter having intentionally miss-matched filter parameters to that of the modulator filter.
Claim 3
Dependent Claim
24 words
The method as in claim 1 wherein the clock modulated signals are two separate signals, with one having different amplitude than the other signal.
Claim 4
Dependent Claim
21 words
The method as in claim 1 wherein the clock modulated signals have changeable distance between the rising edges and falling edges.
Claim 5
Dependent Claim
22 words
The method as in claim 1 wherein one clock modulated signal has a shorter time duration than the other clock modulated signal.
Claim 6
Dependent Claim
33 words
The method as in claim 1 wherein the signal transmitter comprises of a linear amplifier, a non-linear amplifier and a selector switch for selection of the linearly amplified or the non-linearly amplified signal.
Claim 7
Dependent Claim
16 words
The method as in claim 1 wherein the clock modulated signals comprise two distinct signal formats.
Claim 8
Independent Claim
117 words
A system comprising: an unit for providing a Bit Rate Agile (BRA) data signal to a clock modulator; a clock modulator generating a first shaped and a second shaped BRA clock modulated signal and providing said first and second shaped BRA clock modulated signals to a selector switch; a said selector switch for selecting the first or the second clock modulated signal and connecting the selected signal modulated to a signal transmitter filter; a said transmitter filter band limiting the said modulated signals; a signal transmitter transmitting the clock modulated bandlimited signals; a receiver and demodulator for reception and demodulation of clock modulated signals; and a Bit Rate Agile (BRA) demodulator filter for filtering the received signals.
Claim 9
Independent Claim
117 words
A system comprising: an unit for providing a Bit Rate Agile (BRA) data signal to a clock modulator; a clock modulator generating a first shaped and a second shaped BRA clock modulated signal and providing said first and second shaped BRA clock modulated signals to a selector switch; a said selector switch for selecting the first or the second clock modulated signal and connecting the selected signal modulated to a signal transmitter filter; a said transmitter filter band limiting the said modulated signals; a signal transmitter transmitting the clock modulated bandlimited signals; a receiver and demodulator for reception and demodulation of clock modulated signals; and a Bit Rate Agile (BRA) demodulator filter for filtering the received signals.
Claim 10
Dependent Claim
31 words
The method as in claim 7 wherein the Bit Rate Agile (BRA) demodulator filter for filtering the received clock modulated signals is intentionally miss-matched filter to that of the transmitter filter.
Claim 11
Dependent Claim
28 words
The method as in claim 7 wherein the two shaped clock signals comprise two distinct signal formats, with one signal having shorter time duration than the other signal.
Claim 12
Dependent Claim
28 words
The method as in claim 7 wherein the two shaped lock signals comprise two distinct signal formats, with one signal having larger signal amplitude than the other signal.
Claim 13
Independent Claim
107 words
A system comprising: a data unit for providing a data signal to two clock generators; a first clock generator generating a first shaped, non-symmetrical format clock signal and providing the first shaped clock signal to a selector switch; a second clock generator generating a second shaped clock signal and providing the second shaped clock signal to the said selector switch; said selector switch for selecting the first or the second shaped clock signal, having a first input interface port coupled to data controller signals, and a set of input ports coupled to the shaped clock signals and an output interface port coupled to said selector switch output.
Claim 14
Independent Claim
107 words
A system comprising: a data unit for providing a data signal to two clock generators; a first clock generator generating a first shaped, non-symmetrical format clock signal and providing the first shaped clock signal to a selector switch; a second clock generator generating a second shaped clock signal and providing the second shaped clock signal to the said selector switch; said selector switch for selecting the first or the second shaped clock signal, having a first input interface port coupled to data controller signals, and a set of input ports coupled to the shaped clock signals and an output interface port coupled to said selector switch output.
Claim 15
Dependent Claim
28 words
The method as in claim 11 wherein the two shaped clock signals comprise two distinct signal formats, with one signal having larger signal amplitude than the other signal.
Claim 16
Dependent Claim
64 words
The method as in claim 11 wherein the said output interface port coupled to said selector switch output provides the selected shaped signal to a transmitter filter and a transmitter transmitting the clock modulated bandlimited signals and to a receiver and demodulator for reception and demodulation of clock modulated signal and to a Bit Rate Agile (BRA) demodulator filter for filtering the received signals.
Claim 17
Dependent Claim
82 words
The method as in claim 11 wherein the said output interface port coupled to said selector switch output provides the selected shaped signal to a modulator filter and a signal transmitter transmitting the signal to a receiver and demodulator for reception and demodulation of clock modulated signals and to a Bit Rate Agile (BRA) demodulator filter for filtering the received signals, wherein the demodulator filter for filtering the received clock modulated signals is intentionally miss-matched filter to that of the modulator filter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-07-16 | 2011-01-15 | 2011-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-07-16 | 2015-01-15 | 2015-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-07-16 | 2019-01-15 | 2019-07-17 | $7700.00 | Window Closed / Lapsed |