US7239257B1
Expired / Lapsed
US
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Hardware efficient digital control loop architecture for a power converter
Assignee: Intersil Americas LLC
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Filing: 2006-03-16
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Granted: 2007-07-03
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Expires: 2026-03-16
Abstract
Abstract A power converter including a hardware efficient control loop architecture. Error detection circuitry may generate an error signal based on the difference between a power converter output voltage and a reference voltage. An oversampling ADC may digitize the error signal. The transfer function associated with the ADC may include quantization levels spaced at non-uniform intervals away from a center code. A digital filter may calculate the average of the digitized error signal. A nonlinear requantizer may reduce the number of codes corresponding to the output of the digital filter. A proportional integral derivative (PID) unit may multiply the output of the nonlinear requantizer by PID coefficients to generate a PID duty cycle command, and a gain compensation unit may dynamically adjust the PID coefficients to maintain a constant control loop gain. A noise-shaped truncation unit including a multi-level error-feedback delta sigma modulator may reduce the resolution of the PID duty cycle command.
Inventors
- 👤 Mark A. Alexander
- 👤 Douglas E. Heineman
- 👤 Kenneth W. Fernald
- 👤 Scott K. Herrington
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:30
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/10; H02M3/145; H02M3/155; H02M3/156; H02M3/157
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
58 words
A power converter comprising: error detection circuitry configured to generate an error signal based on the difference between a power converter output voltage and a reference voltage; an oversampling analog-to-digital converter (ADC) configured to digitize the error signal; wherein a transfer function associated with the ADC includes quantization levels spaced at non-uniform intervals away from a center code.
Claim 2
Dependent Claim
58 words
A power converter comprising: error detection circuitry configured to generate an error signal based on the difference between a power converter output voltage and a reference voltage; an oversampling analog-to-digital converter (ADC) configured to digitize the error signal; wherein a transfer function associated with the ADC includes quantization levels spaced at non-uniform intervals away from a center code.
Claim 3
Dependent Claim
23 words
The power converter of claim 1 , wherein the quantization levels are spaced at increasing powers of 2 away from the center code.
Claim 4
Dependent Claim
47 words
The power converter of claim 1 , wherein the quantization levels are spaced at increasing powers of 2 away from the center code, with the exception that at least one of the quantization levels spaced at increasing powers of 2 away from the center code is removed.
Claim 5
Dependent Claim
22 words
The power converter of claim 1 , further comprising a digital filter configured to calculate the average of the digitized error signal.
Claim 6
Dependent Claim
54 words
The power converter of claim 1 , further comprising: a digital filter configured to calculate the average of the digitized error signal; and a nonlinear requantizer configured to reduce the number of codes corresponding to the output of the digital filter to values that are spaced at non-uniform intervals away from the center code.
Claim 7
Dependent Claim
43 words
The power converter of claim 5 , wherein the nonlinear requantizer is configured to reduce the number of codes corresponding to the output of the digital filter to values that are represented as a sum of a reduced number of powers of 2.
Claim 8
Dependent Claim
42 words
The power converter of claim 5 , wherein the nonlinear requantizer is configured to reduce the number of codes corresponding to the output of the digital filter to values that are spaced at increasing powers of 2 away from the center code.
Claim 9
Dependent Claim
97 words
The power converter of claim 1 , further comprising: a digital filter configured to calculate the average of the digitized error signal; a nonlinear requantizer configured to reduce the number of codes corresponding to the output of the digital filter to values that are spaced at non-uniform intervals away from the center code; a proportional integral derivative (PID) unit configured to multiply the output of the nonlinear requantizer by PID coefficients to generate a PID duty cycle command; and a gain compensation unit configured to dynamically adjust the PID coefficients to maintain a constant control loop gain.
Claim 10
Dependent Claim
40 words
The power converter of claim 8 , wherein, in response to gain changes in an analog front-end of the power converter, the gain compensation unit is configured to dynamically adjust the PID coefficients to maintain a constant control loop gain.
Claim 11
Dependent Claim
40 words
The power converter of claim 8 , wherein, in response to gain changes in a power stage of the power converter, the gain compensation unit is configured to dynamically adjust the PID coefficients to maintain a constant control loop gain.
Claim 12
Dependent Claim
77 words
The power converter of claim 8 , wherein the gain compensation unit includes a feed-forward gain (FFG) correction unit configured to measure an input voltage to a power stage of the power converter to detect gain changes in the power stage, wherein, in response to detecting gain changes in the power stage, the FFG correction unit is further configured to process the PID duty cycle command using a lookup table to maintain a constant control loop gain.
Claim 13
Dependent Claim
31 words
The power converter of claim 11 , wherein the PID duty cycle command is processed using lookup table FFG correction constants that are encoded in Canonic Signed Digit (CSD) ternary form.
Claim 14
Dependent Claim
119 words
The power converter of claim 1 , further comprising: a digital filter configured to calculate the average of the digitized error signal; a nonlinear requantizer configured to reduce the number of codes corresponding to the output of the digital filter to values that are spaced at non-uniform intervals away from the center code; a proportional integral derivative (PID) unit configured to multiply the output of the nonlinear requantizer by PID coefficients to generate a PID duty cycle command; a gain compensation unit configured to dynamically adjust the PID coefficients to maintain a constant control loop gain; and a noise-shaped truncation unit including a multi-level error-feedback delta sigma modulator configured to reduce the resolution of the PID duty cycle command.
Claim 15
Dependent Claim
49 words
The power converter of claim 1 , further comprising an analog front-end including at least a programmable gain amplifier (PGA) and a reference voltage generator, wherein the PGA is operable to maximize the applied dynamic range of the reference voltage generator, the error detection circuitry, and the oversampling ADC.
Claim 16
Dependent Claim
56 words
The power converter of claim 1 , further comprising an attenuator circuit coupled to the output of the power converter and configured to attenuate the power converter output voltage, wherein the error detection circuitry is configured to generate an error signal based on the difference between the attenuated power converter output voltage and a reference voltage.
Claim 17
Independent Claim
66 words
A method for operating a power converter, the method comprising: generating an error signal based on the difference between a power converter output voltage and a reference voltage; digitizing the error signal using an oversampling analog-to-digital converter (ADC); wherein, in said digitizing the error signal, implementing a transfer function associated with the ADC that includes quantization levels spaced at non-uniform intervals away from a center code.
Claim 18
Independent Claim
66 words
A method for operating a power converter, the method comprising: generating an error signal based on the difference between a power converter output voltage and a reference voltage; digitizing the error signal using an oversampling analog-to-digital converter (ADC); wherein, in said digitizing the error signal, implementing a transfer function associated with the ADC that includes quantization levels spaced at non-uniform intervals away from a center code.
Claim 19
Dependent Claim
36 words
The method of claim 16 , wherein, in said digitizing the error signal, implementing a transfer function associated with the ADC that includes quantization levels spaced at increasing powers of 2 away from the center code.
Claim 20
Dependent Claim
47 words
The method of claim 16 , further comprising: calculating the average of the digitized error signal and generating a modified error signal; and requantizing the modified error signal to reduce the number of codes to values that are spaced at non-uniform intervals away from the center code.
Claim 21
Dependent Claim
34 words
The method of claim 18 , further comprising requantizing the modified error signal to reduce the number of codes to values that are spaced at increasing powers of 2 away from the center code.
Claim 22
Dependent Claim
74 words
The method of claim 16 , further comprising: calculating the average of the digitized error signal and generating a modified error signal; requantizing the modified error signal to reduce the number of codes to values that are spaced at non-uniform intervals away from the center code; multiplying the requantized error signal by PID coefficients to generate a PID duty cycle command; and dynamically adjusting the PID coefficients to maintain a constant control loop gain.
Claim 23
Dependent Claim
89 words
The method of claim 16 , further comprising: calculating the average of the digitized error signal and generating a modified error signal; requantizing the modified error signal to reduce the number of codes to values that are spaced at non-uniform intervals away from the center code; multiplying the requantized error signal by PID coefficients to generate a PID duty cycle command; dynamically adjusting the PID coefficients to maintain a constant control loop gain; and performing noise-shaped word length truncation to reduce the resolution of the PID duty cycle command.
Claim 24
Dependent Claim
172 words
A power distribution system including a plurality of power converters, wherein each power converter comprises: error detection circuitry configured to generate an error signal based on the difference between a power converter output voltage and a reference voltage; an oversampling analog-to-digital converter (ADC) configured to digitize the error signal, wherein a transfer function associated with the ADC includes quantization levels spaced at non-uniform intervals away from a center code; a digital filter configured to calculate the average of the digitized error signal; a nonlinear requantizer configured to reduce the number of codes corresponding to the output of the digital filter to values that are spaced at non-uniform intervals away from the center code; a proportional integral derivative (PID) unit configured to multiply the output of the nonlinear requantizer by PID coefficients to generate a PID duty cycle command; a gain compensation unit configured to dynamically adjust the PID coefficients to maintain a constant control loop gain; and a noise-shaped truncation unit configured to reduce the resolution of the PID duty cycle command.
Claim 25
Dependent Claim
172 words
A power distribution system including a plurality of power converters, wherein each power converter comprises: error detection circuitry configured to generate an error signal based on the difference between a power converter output voltage and a reference voltage; an oversampling analog-to-digital converter (ADC) configured to digitize the error signal, wherein a transfer function associated with the ADC includes quantization levels spaced at non-uniform intervals away from a center code; a digital filter configured to calculate the average of the digitized error signal; a nonlinear requantizer configured to reduce the number of codes corresponding to the output of the digital filter to values that are spaced at non-uniform intervals away from the center code; a proportional integral derivative (PID) unit configured to multiply the output of the nonlinear requantizer by PID coefficients to generate a PID duty cycle command; a gain compensation unit configured to dynamically adjust the PID coefficients to maintain a constant control loop gain; and a noise-shaped truncation unit configured to reduce the resolution of the PID duty cycle command.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-07-02 | 2011-01-01 | 2011-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-07-02 | 2015-01-01 | 2015-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-07-02 | 2019-01-01 | 2019-07-03 | $7700.00 | Window Closed / Lapsed |