US6958721B2
Expired / Lapsed
US
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Matched delay line voltage converter
Assignee: University of Colorado Boulder
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Filing: 2003-09-18
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Granted: 2005-10-25
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Expires: 2023-09-18
Abstract
Abstract A method and apparatus for measuring or converting voltage, the method comprising: applying an input voltage to a primary delay line; applying a reference voltage to a timer delay line; propagating a delay signal through the primary delay line; propagating a timer signal through the timer delay line; establishing a sampling period based on the timer signal propagation; and measuring an extent of delay signal propagation along the primary delay line during the established sampling period, the measured signal propagation extent being indicative of a difference between the input voltage and the reference voltage.
Inventors
- 👤 Michael Vincent
- 👤 Dragan Maksimovic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:03
CPC Classifications
G; G04; G04F; G04F10/00; G04F10/005; H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/502; H03M1/10; H03M1/1009
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
112 words
An analog-to-digital converter (ADC) comprising: a source of an input voltage; a source of a reference voltage; a primary delay line connected to said source of an input voltage, and having a delay signal input and a plurality of tap outputs; a timer delay line connected to said source of a reference voltage and having a timer signal input and a timer signal output; a delay signal source connected to said delay signal input and said timer delay signal input, and a digital output circuit coupled to said tap outputs and said timer signal output to provide a digital output indicative of a difference between said input voltage and said reference voltage.
Claim 2
Dependent Claim
112 words
An analog-to-digital converter (ADC) comprising: a source of an input voltage; a source of a reference voltage; a primary delay line connected to said source of an input voltage, and having a delay signal input and a plurality of tap outputs; a timer delay line connected to said source of a reference voltage and having a timer signal input and a timer signal output; a delay signal source connected to said delay signal input and said timer delay signal input, and a digital output circuit coupled to said tap outputs and said timer signal output to provide a digital output indicative of a difference between said input voltage and said reference voltage.
Claim 3
Dependent Claim
15 words
The ADC of claim 1 whereln said ADC is implemented entirely with digital logic gates.
Claim 4
Dependent Claim
12 words
The ADC of claim 1 wherein said ADC includes no analog components.
Claim 5
Dependent Claim
22 words
The ADC of claim 1 wherein said primary delay line and said timer delay line are incorporated into a single integrated circuit.
Claim 6
Dependent Claim
16 words
The ADC of claim 1 wherein said primary delay line comprises a plurality of delay cells.
Claim 7
Dependent Claim
16 words
The ADC of claim 5 wherein each of said delay cells comprises a digital logic element.
Claim 8
Dependent Claim
20 words
The ADC of claim 1 wherein said timer delay line is substantially one-half the length of said primary delay line.
Claim 9
Dependent Claim
29 words
The ADC of claim 1 wherein said delay signal source simultaneously provides a delay signal to said delay signal input and a timer signal to said timer signal input.
Claim 10
Dependent Claim
24 words
The ADC of claim 8 wherein said delay signal and said timer signal as provided by said delay signal source are the same signal.
Claim 11
Dependent Claim
16 words
The ADC of claim 1 wherein said digital output circuit comprises an array of flip-flop circuits.
Claim 12
Dependent Claim
13 words
The ADC of claim 1 wherein said digital output circuit includes a counter.
Claim 13
Dependent Claim
14 words
The ADC of claim 1 wherein said digital output circuit includes a shift register.
Claim 14
Dependent Claim
15 words
The ADC of claim 1 wherein said primary delay line is a flat delay line.
Claim 15
Dependent Claim
15 words
The ADC of claim 1 wherein said primary delay line is a folded delay line.
Claim 16
Dependent Claim
26 words
The ADC of claim 1 wherein said primary delay line comprises a number of delay cells corresponding to the desired least significant bit (LSB) voltage step-size.
Claim 17
Dependent Claim
33 words
The ADC of claim 1 wherein said primary delay line comprises a number of delay cells smaller than the number of cells required to produce the desired least significant bit (LSB) voltage step-size.
Claim 18
Dependent Claim
15 words
The ADC of claim 1 wherein said timer delay line is a flat delay line.
Claim 19
Dependent Claim
15 words
The ADC of claim 1 wherein said timer delay line is a folded delay line.
Claim 20
Dependent Claim
15 words
The ADC of claim 1 wherein said digital output circuit includes a gain calibration circuit.
Claim 21
Dependent Claim
15 words
The ADC of claim 1 wherein said digital output circuit includes a mismatch correction circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2008-10-24 | 2009-04-25 | 2009-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-10-24 | 2013-04-25 | 2013-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-10-24 | 2017-04-25 | 2017-10-25 | $7700.00 | Window Closed / Lapsed |