Linear phase finite impulse response filter with pre-addition

Claim 2

A linear phase finite impulse response (FIR) filter having a symmetrical filter coefficient set for receiving an oversampled digital data bit stream from an analog modulator and then convolving and decimating the data to a higher resolution and lower sampling rate, comprising: a pre-addition circuit for summing the input data values associated with each of the symmetrical coefficients, such that a summed data value can be output for each set of said symmetrical coefficients wherein at least one of said summed values is a value of "2" or greater; an encoding device for encoding the summed data into a multiplication control format restricted to the data values of "+1", "0", or "-1"; a multiplication engine for operating in conjunction with said encoded control format values and operable to pass the associated symmetrical coefficient through to an output when a "+1" value is encoded, output a null value when a "0" is encoded, and output the inverse of the associated symmetrical coefficient when a value of "-1" is encoded; and an accumulator for accumulating the output of the multiplication engine over a sampling cycle for a given set of input data values in a sampling cycle.

Claim 3

The filter of claim 1, wherein said pre-addition circuit comprises: a buffer for buffering the oversampled digital data stream for one sampling cycle; and a summation circuit for selecting and summing pairs of said buffered data associated with a given one of the symmetrical coefficients that is input to said multiplication engine to provide on the output of said summation circuit the summing data associated with the symmetrical coefficient input to said multiplication engine.

Claim 4

The filter of claim 1, wherein said encoding device comprises an offset device for adding a multiple of the values "+1" or "-1" to said summed data to force the value to a maximum of "+1" and a minimum of "-1".

Claim 5

The filter of claim 1, wherein said multiplication engine operates at one-half the product of the number of filter coefficients and the output sampling frequency.

Claim 6

The filter of claim 1, wherein the digital data bit stream is comprised of a multi-level single-bit data stream.

Claim 7

The filter of claim 5, and further comprising a non-linearity correction device for correcting for non-linearities in the multi-level input data stream.

Claim 8

A linear phase finite impulse response (FIR) filter having a symmetrical filter coefficient set for receiving an oversampled single-bit multi-level data stream with the levels {1,0, -1}, from an analog modulator and then convolving and decimating the data to a higher resolution and lower sampling rate, comprising: first and second processing paths, said first processing path for processing the "+1" term of the multi-level data and said second processing path for processing the "-1" term of the input data; a mapping device for mapping a "0" to said first path when the data value is a "-1" value and mapping a "0" to said second path when the data is a "+1" value; each of said first and second processing paths having: a pre-addition circuit for summing the input data values for the associated first and second processing paths, which data values are associated with each of the symmetrical coefficients, such that a summed data value can be output for each set of symmetrical coefficients for each of the first and second processing paths, an encoding device for encoding the summed data into a format restricted to a data value format of "+1", "0" or "-1" values wherein at least one of said summed values is a value of "2" or greater, a multiplication engine for operating in conjunction with said encoded format and operable to pass the associated symmetrical coefficient through said multiplication engine when a "+1" encoded value is output, a null value output from said multiplication engine when a "0" encoded format value is present and invert the coefficient value when the encoded format value is a "-1" value, an accumulator for accumulating the outputs of said multiplication engine over a given sampling cycle at the output sampling rate; and a summing circuit for summing the outputs of said accumulators for said first and second processing paths.

Claim 9

A linear phase finite impulse response (FIR) filter having a symmetrical filter coefficient set for receiving an oversampled single-bit multi-level data stream with the levels {1,0, -1}, from an analog modulator and then convolving and decimating the data to a higher resolution and lower sampling rate, comprising: first and second processing paths, said first processing path for processing the "+1" term of the multi-level data and said second processing path for processing the "-1" term of the input data; a mapping device for mapping a "0" to said first path when the data value is a "-1" value and mapping a "0" to said second path when the data is a "+1" value; each of said first and second processing paths having: a pre-addition circuit for summing the input data values for the associated first and second processing paths, which data values are associated with each of the symmetrical coefficients, such that a summed data value can be output for each set of symmetrical coefficients for each of the first and second processing paths, an encoding device for encoding the summed data into a format restricted to a data value format of "+1", "0" or "-1" values wherein at least one of said summed values is a value of "2" or greater, a multiplication engine for operating in conjunction with said encoded format and operable to pass the associated symmetrical coefficient through said multiplication engine when a "+1" encoded value is output, a null value output from said multiplication engine when a "0" encoded format value is present and invert the coefficient value when the encoded format value is a "-1" value, an accumulator for accumulating the outputs of said multiplication engine over a given sampling cycle at the output sampling rate; and a summing circuit for summing the outputs of said accumulators for said first and second processing paths.

Claim 10

The filter of claim 7, wherein said pre-addition circuits for each of said first and second processing paths each comprise: a buffer for buffering the oversampled digital data bit stream for one sampling cycle; and a summation circuit for selecting pairs of said buffered data associated with a given one of the symmetrical coefficients that is input to said multiplication engine to provide on the output of said summation circuit the summing data associated with the symmetrical coefficient input to said multiplication engine.

Claim 11

The filter of claim 7, wherein said multiplication engines and said accumulators in said first and second processing path operate at approximately one-half the product of the number of filter coefficients and the output sampling frequency.

Claim 12

The filter of claim 7, and further comprising a correction circuit for multiplying the output of said accumulator by a correction factor, which correction factor is a pre-determined correction factor that is operable to correct for non-linearities in the input multi-level data stream, which correction factor is only associated with the "-1" term.

Claim 13

The filter of claim 7, wherein said encoding device comprises: a first offset device for offsetting the values output by said pre-addition circuit in said first processing path by a value of "-1", such that a value of "-1" is added to the output of said pre-addition circuit in said first processing path; and a second offset device for offsetting the summed data output by said pre-addition circuit in said second processing path by adding a value of "+1" to said summed data value of said pre-addition circuit.

Claim 14

The filter of claim 11, wherein said second offset device is comprised of an absolute value device for taking the absolute value of the data prior to input to said pre-addition circuit in said second processing path and a summation device for summing the value of "-1" with the output of said pre-addition circuit in said second processing path.

Claim 15

The filter of claim 11, wherein said summing circuit is operable to subtract the output of said accumulator in said second processing path from the output of said accumulator in said first processing path.

Claim 16

A data converter for converting an analog signal to a digital signal and having an analog modulator for receiving an input analog signal and converting it to an oversampled digital data bit stream and a linear finite impulse response (FIR) filter, the FIR filter having a symmetrical filter coefficient set for receiving the oversampled digital data bit stream from the analog modulator and then convolving and decimating the data to a higher resolution and lower sampling rate, comprising: a pre-addition circuit for summing the input data values associated with each of the symmetrical coefficients, such that a summed data value can be output for each set of said symmetrical coefficients wherein at least one of said summed values is a value of "2" or greater; an encoding device for encoding the summed data into a multiplication control format restricted to the data values of "+1", "0", or "-1"; a multiplication engine for operating in conjunction with said encoded control format values and operable to pass the associated symmetrical coefficient through to an output when a "+1" value is encoded, output a null value when a "0" is encoded, and output the inverse of the associated symmetrical coefficient when a value of "-1" is encoded; and an accumulator for accumulating the output of the multiplication engine over a sampling cycle for a given set of input data values in a sampling cycle.

Claim 17

A data converter for converting an analog signal to a digital signal and having an analog modulator for receiving an input analog signal and converting it to an oversampled digital data bit stream and a linear finite impulse response (FIR) filter, the FIR filter having a symmetrical filter coefficient set for receiving the oversampled digital data bit stream from the analog modulator and then convolving and decimating the data to a higher resolution and lower sampling rate, comprising: a pre-addition circuit for summing the input data values associated with each of the symmetrical coefficients, such that a summed data value can be output for each set of said symmetrical coefficients wherein at least one of said summed values is a value of "2" or greater; an encoding device for encoding the summed data into a multiplication control format restricted to the data values of "+1", "0", or "-1"; a multiplication engine for operating in conjunction with said encoded control format values and operable to pass the associated symmetrical coefficient through to an output when a "+1" value is encoded, output a null value when a "0" is encoded, and output the inverse of the associated symmetrical coefficient when a value of "-1" is encoded; and an accumulator for accumulating the output of the multiplication engine over a sampling cycle for a given set of input data values in a sampling cycle.

Claim 18

The filter of claim 14, wherein said pre-addition circuit comprises: a buffer for buffering the oversampled digital data stream for one sampling cycle; and a summation circuit for selecting and summing pairs of said buffered data associated with a given one of the symmetrical coefficients that is input to said multiplication engine to provide on the output of said summation circuit the summing data associated with the symmetrical coefficient input to said multiplication engine.

Claim 19

The filter of claim 14, wherein said encoding device comprises an offset device for adding a multiple of the values "+1" or "-1" to said summed data to force the value to a maximum of "+1" and a minimum of "-1".

Claim 20

The filter of claim 14, wherein the digital data bit stream is comprised of a multi-level single-bit data stream.

Claim 21

The filter of claim 17, and further comprising a non-linearity correction device for correcting for non-linearities in the multi-level input data stream.

Claim 22

A data converter for converting an analog signal to a digital signal and having an analog modulator for receiving an input analog signal and converting it to an oversampled single-bit multi-level data bit stream and a linear finite impulse response (FIR) filter, the FIR filter having symmetrical filter coefficient set for receiving the oversampled single-bit multi-level data stream with the levels {1,0, -1}, from an analog modulator and then convolving and decimating the data to a higher resolution and lower sampling rate, comprising: first and second processing paths, said first processing path for processing the "+1" term of the multi-level data and said second processing path for processing the "-1" term of the input data; a mapping device for mapping a "0" to said first path when the data value is a "-1" value and mapping a "0" to said second path when the data is a "+1" value; each of said first and second processing paths having: a pre-addition circuit for summing the input data values for the associated first and second processing paths, which data values are associated with each of the symmetrical coefficients, such that a summed data value can be output for each set of symmetrical coefficients for each of the first and second processing paths, an encoding device for encoding the summed data into a format restricted to a format of "+1", "0" or "-1" values, a multiplication engine for operating in conjunction with said encoded format and operable to pass the associated symmetrical coefficient through said multiplication engine when a "+1" encoded value is output, a null value output from said multiplication engine when a "0" encoded format value is present and invert the coefficient value when the encoded format value is a "-1" value, an accumulator for accumulating the outputs of said multiplication engine over a given sampling cycle at the output sampling rate; and a summing circuit for summing the outputs of said accumulators for said first and second processing paths.

Claim 23

A data converter for converting an analog signal to a digital signal and having an analog modulator for receiving an input analog signal and converting it to an oversampled single-bit multi-level data bit stream and a linear finite impulse response (FIR) filter, the FIR filter having symmetrical filter coefficient set for receiving the oversampled single-bit multi-level data stream with the levels {1,0, -1}, from an analog modulator and then convolving and decimating the data to a higher resolution and lower sampling rate, comprising: first and second processing paths, said first processing path for processing the "+1" term of the multi-level data and said second processing path for processing the "-1" term of the input data; a mapping device for mapping a "0" to said first path when the data value is a "-1" value and mapping a "0" to said second path when the data is a "+1" value; each of said first and second processing paths having: a pre-addition circuit for summing the input data values for the associated first and second processing paths, which data values are associated with each of the symmetrical coefficients, such that a summed data value can be output for each set of symmetrical coefficients for each of the first and second processing paths, an encoding device for encoding the summed data into a format restricted to a format of "+1", "0" or "-1" values, a multiplication engine for operating in conjunction with said encoded format and operable to pass the associated symmetrical coefficient through said multiplication engine when a "+1" encoded value is output, a null value output from said multiplication engine when a "0" encoded format value is present and invert the coefficient value when the encoded format value is a "-1" value, an accumulator for accumulating the outputs of said multiplication engine over a given sampling cycle at the output sampling rate; and a summing circuit for summing the outputs of said accumulators for said first and second processing paths.

Claim 24

The filter of claim 19, wherein said pre-addition circuits for each of said first and second processing paths each comprise: a buffer for buffering the oversampled digital data bit stream for one sampling cycle; and a summation circuit for selecting pairs of said buffered data associated with a given one of the symmetrical coefficients that is input to said multiplication engine to provide on the output of said summation circuit the summing data associated with the symmetrical coefficient input to said multiplication engine.

Claim 25

The filter of claim 19, wherein said encoding device comprises: a first offset device for offsetting the values output by said pre-addition circuit in said first processing path by a value of "-1", such that a value of "-1" is added to the output of said pre-addition circuit in said first processing path; and a second offset device for offsetting the summed data output by said pre-addition circuit in said second processing path by adding a value of "+1" to said summed data value of said pre-addition circuit.

Claim 26

The filter of claim 21, wherein said summing circuit is operable to subtract the output of said accumulator in said second processing path from the output of said accumulator in said first processing path.

Claim 27

The filter of claim 21, wherein said second offset device is comprised of an absolute value device for taking the absolute value of the data prior to input to said pre-addition circuit in said second processing path and a summation device for summing the value of "-1" with the output of said pre-addition circuit in said second processing path.

Claim 30

The method of claim 24, wherein the step of summing the input data values in the pre-addition circuit comprises the steps of: buffering the oversampled digital data stream for one sampling cycle in a buffer; and selecting and summing pairs of the buffer data associated with a given one of the symmetrical coefficients that is input to the multiplication engine to provide on an output the summing data associated with the symmetrical coefficient input to the multiplication engine.

Claim 31

The method of claim 24, wherein the encoding device is operable to add a multiple of the values "+1" or "-1" to the summed data to force the value to a maximum of "+1" and a minimum of "-1".

Claim 32

The method of claim 24, wherein the multiplication engine operates at one-half the product of the number of filter coefficients and the output sampling frequency.

Claim 33

The method of claim 24, where the digital data bit stream is comprised of a multi-level single-bit data stream.

Claim 34

The method of claim 28, and further comprising correcting for nonlinearities in the multi-level input data stream.

Claim 35

A linear phase finite impulse response (FIR) filter having a symmetrical filter coefficient set for receiving a three-state multi-bit oversampled digital data bit stream from an analog modulator having values {-1, 0, +1} and then convolving and decimating the data to a high resolution and lower sampling rate, comprising: a parsing circuit for parsing the three-state input data to first and second paths, each with two states; a pre-addition circuit associated with each of said paths for summing the two state input data values in said associated path and associated with each of the symmetrical coefficients, such that a summed data value can be output for each set of said symmetrical coefficients for said associated path to provide three states for each of said first and second paths; an offset device for each of said first and second paths for restricting the data values of each of said three states to "+1, " "0" and "-1"; a FIR filter engine in each of said first and second paths for filtering the three-state output of said pre-addition circuit and operating at substantially one-half clock rate of the oversampled digital data bit stream; each of said first and second paths being non-linear; and a combiner device for combining the output of each of said FIR filter engines in said first and second paths to provide a linear output.

Claim 36

A linear phase finite impulse response (FIR) filter having a symmetrical filter coefficient set for receiving a three-state multi-bit oversampled digital data bit stream from an analog modulator having values {-1, 0, +1} and then convolving and decimating the data to a high resolution and lower sampling rate, comprising: a parsing circuit for parsing the three-state input data to first and second paths, each with two states; a pre-addition circuit associated with each of said paths for summing the two state input data values in said associated path and associated with each of the symmetrical coefficients, such that a summed data value can be output for each set of said symmetrical coefficients for said associated path to provide three states for each of said first and second paths; an offset device for each of said first and second paths for restricting the data values of each of said three states to "+1, " "0" and "-1"; a FIR filter engine in each of said first and second paths for filtering the three-state output of said pre-addition circuit and operating at substantially one-half clock rate of the oversampled digital data bit stream; each of said first and second paths being non-linear; and a combiner device for combining the output of each of said FIR filter engines in said first and second paths to provide a linear output.

Claim 37

The filter of claim 30, wherein one of the three states in the input data stream causes a non-linearity and wherein said one state is restricted to one of said first and second paths and further comprising a correction circuit for correcting said non-linearity within said associated first or second paths.

Claim 38

The filter of claim 31, wherein said correction circuit is disposed after said filter.