US5500811A
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Finite impulse response filter
Assignee: Microunity Systems Engineering Inc
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Filing: 1995-01-23
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Granted: 1996-03-19
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Expires: 2015-01-23
Abstract
Abstract A compact Finite Impulse Response (FIR) filter using one or both of a compact address sequencer and a compact multiplier/accumulator. The address sequencer exploits certain symmetry properties existing between different phases of a polyphase FIR filter in order to reduce coefficient storage and simplify address sequencing. The multiplier/accumulator is capable of performing two multiply/accumulate operations per clock cycle, avoiding in certain instances the need to add a second multiplier/accumulator. The area required to realize a FIR filter for performing real-time filter is therefore reduced.
Inventors
- 👤 Alan G. Corry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:50
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/0248; H03H17/0264; H03H17/0273; H03H17/0275; H03H17/06
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
89 words
A method of calculating output data points of a polyphase Finite Impulse Response filter using a complex multiplier, comprising the steps of: a) applying to the complex multiplier a pair of constants K 1 and K 2 different from but related to a pair of filter coefficients A i and A j ; b) applying to the complex multiplier a pair of input operands X i and X j ; and c) operating the complex multiplier to form the quantity A i X i +A j X j .
Claim 2
Independent Claim
89 words
A method of calculating output data points of a polyphase Finite Impulse Response filter using a complex multiplier, comprising the steps of: a) applying to the complex multiplier a pair of constants K 1 and K 2 different from but related to a pair of filter coefficients A i and A j ; b) applying to the complex multiplier a pair of input operands X i and X j ; and c) operating the complex multiplier to form the quantity A i X i +A j X j .
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein K 1 =(A i +A j )/2 and K 2 =(A i -A j )/2.
Claim 4
Dependent Claim
24 words
The method of claim 2, comprising the further step of: d) repeating step a) through step c) with different index values i and j.
Claim 5
Dependent Claim
34 words
The method of claim 3, wherein step b) comprises applying X i to a first operand input of the complex multiplier and applying X j to a second operand input of the complex multiplier.
Claim 6
Dependent Claim
36 words
The method of claim 4, comprising the further step of: e) repeating step a) through step c) with the same index values i and j as during a previous iteration of step a) through step c).
Claim 7
Dependent Claim
34 words
The method of claim 5, wherein step e) comprises applying X i to said second operand input of the complex multiplier and applying X j to said first operand input of the complex multiplier.
Claim 8
Dependent Claim
24 words
The method of claim 3, comprising: d1) repeating step a) through step d) for each of a plurality of sets of index value pairs.
Claim 9
Dependent Claim
34 words
The method of claim 7, wherein step b) comprises applying X i to a first operand input of the complex multiplier and applying X j to a second operand input of the complex multiplier.
Claim 10
Dependent Claim
40 words
The method of claim 8, comprising the further step of: e) repeating step a) through step d) for each of a plurality of sets of index value pairs, with the same index values i and j as during step d1)).
Claim 11
Dependent Claim
34 words
The method of claim 9, wherein step e) comprises applying X i to said second operand input of the complex multiplier and applying X j to said first operand input of the complex multiplier.
Claim 12
Dependent Claim
79 words
The method of claim 10, wherein said plurality is a number N/2 where N is an even number, step d1)) comprising repeating step a) through step d) first for a set S 1 of index value pairs and last for a set S N/2 of index value pairs, and step e) comprising repeating step a) through step d) first for a set S N/2 of index value pairs and last for a set S 1 of index value pairs.
Claim 13
Independent Claim
125 words
A apparatus for calculating output data points of a digital filter comprising: a memory storing a plurality of filter-coefficient-related constants and for storing a plurality of input data points; an address generator connected to said memory; and a complex multiplier/accumulator connected to said memory and having a first input port, a second input port and an output port, said complex multiplier/accumulator receiving at said first input port signals representing a pair of constants different from but related to filter coefficients A i and A j , receiving at said second input port signals representing a pair of input data points X i and X j , and producing at said output port signals representing the quantity A i X i +A j X j .
Claim 14
Independent Claim
125 words
A apparatus for calculating output data points of a digital filter comprising: a memory storing a plurality of filter-coefficient-related constants and for storing a plurality of input data points; an address generator connected to said memory; and a complex multiplier/accumulator connected to said memory and having a first input port, a second input port and an output port, said complex multiplier/accumulator receiving at said first input port signals representing a pair of constants different from but related to filter coefficients A i and A j , receiving at said second input port signals representing a pair of input data points X i and X j , and producing at said output port signals representing the quantity A i X i +A j X j .
Claim 15
Dependent Claim
33 words
The apparatus of claim 12, wherein said complex multiplier/accumulator comprises an array of interconnected basic cells arrayed in rows and columns, each row of said basic cells forming a different intermediate multiply/accumulate result.
Claim 16
Dependent Claim
39 words
The apparatus of claim 13, wherein said complex multiplier/accumulator further comprises a control circuit for generating for each row of said basic cells a select signal in accordance with corresponding single bits of X i and X j .
Claim 17
Dependent Claim
37 words
The apparatus of claim 14, wherein said control circuit further generates for each row of said basic cells a add/subtract signal in accordance with a corresponding single bit of one of X i and X j .
Claim 18
Dependent Claim
109 words
The apparatus of claim 15, wherein each of said basic cells comprises a multiplexer responsive to said select signal for a row of said basic cell for selecting a bit from one of said pair of constants related to filter coefficients Ai and Aj, and a full adder/subtracter receiving a sum input signal and a carry input signal from adjacent basic cells and responsive to said add/subtract signal for said row of said basic cell for adding or subtracting said bit to or from a radix-2 quantity represented by said sum input signal and said carry input signal to produce a sum output signal and a carry output signal.
Claim 19
Dependent Claim
50 words
The apparatus of claim 12, wherein said address generator generates a mux control signal and said complex multiplier/accumulator comprises a multiplexer responsive to said mux control signal for selectively interchanging at said second input port said signals representing said pair of input data points X i and X j .
Claim 20
Dependent Claim
128 words
The apparatus of claim 17, wherein said address generator comprises: first means operating at a first rate R 1 for repeatedly generating a symmetric sequence of binary numbers H 0 , H 2 , . . . , H N-1 where H q =H N-1-q ; second means connected to said first means and operating at a second rate R 2 =MR 1 for repeatedly generating a monotonic sequence of binary numbers L 0 , L 2 , . . . , L M-1 where M is an integer; and third means connected to said first and second means for forming a concatenation HL of one of said symmetric sequence of binary numbers and one of said monotonic sequence of binary numbers as a address for said memory.
Claim 21
Dependent Claim
50 words
The apparatus of claim 18, wherein said first means comprises a binary counter and a plurality of EXOR gates each connected to different output bits of said binary counter and each connected also to a same output bit of said binary counter of greater significance than said different output bits.
Claim 22
Dependent Claim
33 words
The apparatus of claim 19, wherein said second means comprises a modulo-M counter clocked by a clock signal and producing an overflow signal, said overflow signal being connected to clock said binary counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-19 | 1999-09-18 | 2000-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-19 | 2003-09-18 | 2004-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-19 | 2007-09-18 | 2008-03-19 | $7700.00 | Window Closed / Lapsed |