Finite impulse response (fir) filter using a plurality of cascaded digital signal processors (dsps)

Claim 1

An FIR digital filter device which generates M pieces of delayed digital data having mutually different delay times equal to a natural number times a sampling period for digital input data, multiplies said M pieces of delayed digital data and said digital input data by multiplication coefficients, and adds the multiplied results to form output data, said FIR digital filter device comprising a plurality of cascaded digital signal processors each including a delay unit, a multiplier, and a first operation unit for performing algebraic addition, and a second operation unit for performing accumulative addition, wherein said digital input data is transferred in the forward direction through said delay units of said digital signal processors between the forefront stage and the final stage, and is then transferred in the reverse direction through said delay units of the digital signal processors between the final stage and the forefront stage, each of said digital signal processors except for said digital signal processor in the final stage provides said digital input data with the same delay time for the forward and reverse directions, so that said M pieces of delayed digital data are generated, each of said digital signal processors multiplies the operation results obtained by performing the algebraic addition of said delayed digital data and said digital input data having mutually symmetrical delay times with the center of symmetry corresponding to a delay time equal to M/2 times as large as the sampling period, and multiplies the algebraic addition results by said multiplication coefficients through the related multipliers, said digital processor in the final stage multiplies said delayed digital data having the delayed time equal to M/2 times as large as the sampling period when M is an even number, the digital signal processor in the forefront stage adds the multiplied results through the second operation units and outputs the accumulative addition results as carry-over data to the next stage, the digital signal processors in the second and subsequent stages add the results supplied from said second operation units and said carry-over data supplied from the digital signal processor in the previous stage, and output the addition results as carry-over data to the next stage, the digital signal processor in the final stage outputs, as said output data of the FIR digital signal processor, the carry-over data derived from the digital signal processors in the final stage, the digital processor in the final stage delaying the carry-over data by a predetermined sampling period and subjecting said delayed carry-over data to the digital filter operation by said delay unit, said first and second operation units and said multiplier provided therein.