Cascaded delay locked loop circuit

Claim 2

A delay locked loop circuit, comprising: a primary delay line having an input that receives a clock signal and having a plurality of primary output taps; a secondary delay circuit having a plurality of secondary output taps, the secondary delay circuit further having an input that receives a signal from a selected one of the primary output taps; and an output control circuit that selects one or more taps from either the primary delay line or the secondary delay circuit as an output, wherein the output control circuit selects taps based upon an algorithm that: computes a ratio K.C of the clock signal's frequency to a desired output frequency where C is a fractional part and K is an integer part of the ratio; and identifies a sequence of taps constituting a repeating tap cycle at approximately equally spaced delay increments, wherein a j th tap address C j is defined by C j =C j−1 +C.

Claim 3

The apparatus according to claim 1 , wherein the primary delay line has N delay elements with each delay element having a delay of D so that the primary delay line has a total delay of N×D; and wherein the secondary delay circuit has M delay elements with each delay element having a delay of D s so that the secondary delay circuit has a total delay of M×D s .

Claim 4

The apparatus according to claim 2 , wherein MxD s is different than N×D.

Claim 5

The apparatus according to claim 2 , wherein M and N have no common integer factors.

Claim 6

The apparatus according to claim 2 , wherein the secondary delay circuit comprises a passive delay line.

Claim 7

The apparatus according to claim 5 , wherein the passive delay line has a fixed total delay M×D.

Claim 8

The apparatus according to claim 6 , wherein the fixed total delay M×D s is approximately equal to D.

Claim 9

The apparatus according to claim 5 , wherein the passive delay line has an adjustable total delay.

Claim 10

The apparatus according to claim 1 , wherein the primary delay line comprises a plurality of series connected differential delay buffers.

Claim 11

The apparatus according to claim 1 , wherein the secondary delay circuit comprises a plurality of series connected differential delay buffers.

Claim 12

The apparatus according to claim 1 , further comprising a multiplexer disposed between the primary delay line and the secondary delay circuit, and wherein the selected one of the primary output taps is connected to the secondary delay line by the multiplexer.

Claim 13

The apparatus according to claim 1 , wherein the output control circuit comprises a multiplexer receiving signals from at plurality of the primary or secondary output taps as input signals thereto, and control logic for selecting one or more of said input signals as an output of the multiplexer.

Claim 14

The apparatus according to claim 1 , wherein the output control circuit selects an output tap based upon a frequency selection input thereto.

Claim 15

A delay locked loop circuit, comprising: a primary delay line having an input that receives a clock signal, and having an output and having a plurality of N primary output taps from a plurality of delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×D; a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that sets the total delay N×D to a delay that locks the delay locked loop; a secondary delay circuit having an input receiving a signal from a selected one of the N output taps, and a plurality of M secondary output taps at each of a plurality of delay elements each having a delay D s , the secondary delay circuit having a total delay of M×D s ; an output control circuit that selects one or more output taps from either the primary delay line or the secondary delay circuit as an output; and wherein the output control circuit selects taps based upon an algorithm that: computes a ratio K.C of the clock signal's frequency to a desired output frequency where C is a fractional part and K is an integer part of the ratio; and identifies a sequence of taps constituting a repeating tap cycle at approximately equally spaced delay increments, wherein a j th tap address C j is defined by C j =C j−1 C.

Claim 16

A delay locked loop circuit, comprising: a primary delay line having an input that receives a clock signal, and having an output and having a plurality of N primary output taps from a plurality of delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×D; a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that sets the total delay N×D to a delay that locks the delay locked loop; a secondary delay circuit having an input receiving a signal from a selected one of the N output taps, and a plurality of M secondary output taps at each of a plurality of delay elements each having a delay D s , the secondary delay circuit having a total delay of M×D s ; an output control circuit that selects one or more output taps from either the primary delay line or the secondary delay circuit as an output; and wherein the output control circuit selects taps based upon an algorithm that: computes a ratio K.C of the clock signal's frequency to a desired output frequency where C is a fractional part and K is an integer part of the ratio; and identifies a sequence of taps constituting a repeating tap cycle at approximately equally spaced delay increments, wherein a j th tap address C j is defined by C j =C j−1 C.

Claim 17

The apparatus according to claim 14 , further comprising sequentially selecting identified taps to produce an output at time increments approximating K.C×N×D.

Claim 18

The apparatus according to claim 14 , wherein the output control circuit selects taps based upon an algorithm that interpolates fractional tap values by selecting integer tap values that vary as the tap cycle repeats.

Claim 19

A delay locked loop circuit, comprising: a primary delay line having an input that receives a clock signal, and having an output and having a plurality of N output taps from a plurality of delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×D; a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that sets the total delay N×D to a delay that locks the delay locked loop; a plurality of secondary delay circuits, each having an input receiving a signal from one of the N output taps, and each delay element having a plurality of M output taps at each of a plurality of delay elements each having a delay D s , each of the secondary delay circuits having a total delay of M×D s ; an output control circuit that selects one or more taps from either the primary delay line or the secondary delay circuit as an output; and wherein the output control circuit selects taps based upon an algorithm that: computes a ratio K.C of the clock signal's frequency to a desired output frequency where C is a fractional part and K is an integer part of the ratio; and identifies a sequence of taps constituting a repeating tap cycle at approximately equally spaced delay increments, wherein a j th tap address C j is defined by C j =C j−1 C.

Claim 20

A delay locked loop circuit, comprising: a primary delay line having an input that receives a clock signal, and having an output and having a plurality of N output taps from a plurality of delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×D; a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that sets the total delay N×D to a delay that locks the delay locked loop; a plurality of secondary delay circuits, each having an input receiving a signal from one of the N output taps, and each delay element having a plurality of M output taps at each of a plurality of delay elements each having a delay D s , each of the secondary delay circuits having a total delay of M×D s ; an output control circuit that selects one or more taps from either the primary delay line or the secondary delay circuit as an output; and wherein the output control circuit selects taps based upon an algorithm that: computes a ratio K.C of the clock signal's frequency to a desired output frequency where C is a fractional part and K is an integer part of the ratio; and identifies a sequence of taps constituting a repeating tap cycle at approximately equally spaced delay increments, wherein a j th tap address C j is defined by C j =C j−1 C.

Claim 21

The apparatus according to claim 17 , further comprising sequentially selecting identified taps to produce an output at time increments approximating K.C×N×D.

Claim 22

The apparatus according to claim 17 , wherein the output control circuit selects taps based upon an algorithm that interpolates fractional tap values by selecting integer tap values that vary as the tap cycle repeats.

Claim 23

A delay locked loop circuit, comprising: a primary delay line having a plurality of N primary output taps; an N:1 multiplexer receiving signals from each of the N output taps and providing a multiplexer output signal; a passive secondary delay circuit having an input receiving the multiplexer output signal, and having a plurality of M output taps; wherein the primary delay line has a plurality of N delay elements, each having a delay of D so that the primary delay line has a total delay of N×D; and wherein the passive secondary delay circuit has a plurality of M passive delay elements each having a delay D p , the passive secondary delay circuit having a total delay or approximately M×D p , that is set by a control signal; the control signal being determined by a tuning signal from the primary delay line that establishes a global average tuning; and further comprising a memory cell receiving the signal from the primary delay line and storing the global average tuning, and wherein the control signal to the passive secondary delay circuit is received as a fixed value of a global average tuning stored in the memory cell.

Claim 24

A delay locked loop circuit, comprising: a primary delay line having a plurality of N primary output taps; an N:1 multiplexer receiving signals from each of the N output taps and providing a multiplexer output signal; a passive secondary delay circuit having an input receiving the multiplexer output signal, and having a plurality of M output taps; wherein the primary delay line has a plurality of N delay elements, each having a delay of D so that the primary delay line has a total delay of N×D; and wherein the passive secondary delay circuit has a plurality of M passive delay elements each having a delay D p , the passive secondary delay circuit having a total delay or approximately M×D p , that is set by a control signal; the control signal being determined by a tuning signal from the primary delay line that establishes a global average tuning; and further comprising a memory cell receiving the signal from the primary delay line and storing the global average tuning, and wherein the control signal to the passive secondary delay circuit is received as a fixed value of a global average tuning stored in the memory cell.

Claim 25

A delay locked loop circuit, comprising: a primary delay line having a plurality of N primary output taps; an N:1 multiplexer receiving signal from each of the N output taps and providing a multiplexer output signal; a passive secondary delay circuit having an input receiving the multiplexer output signal and having a plurality of M output taps; and wherein the primary delay line has a plurality of N delay elements, each having a delay of D so that the primary delay line has a total delay of N×D; wherein the secondary delay circuit has a plurality of M passive delay elements each having a delay D p , the secondary delay circuit having a total delay of approximately M×D p ; wherein the delay D p of each of the M passive delay elements is set by a corresponding one of M control inputs; and wherein each of the M control inputs receives a control signal comprising a global average tuning value added to one of M individual delay element tuning values.

Claim 26

A delay locked loop circuit, comprising: a primary delay line having a plurality of N primary output taps; an N:1 multiplexer receiving signal from each of the N output taps and providing a multiplexer output signal; a passive secondary delay circuit having an input receiving the multiplexer output signal and having a plurality of M output taps; and wherein the primary delay line has a plurality of N delay elements, each having a delay of D so that the primary delay line has a total delay of N×D; wherein the secondary delay circuit has a plurality of M passive delay elements each having a delay D p , the secondary delay circuit having a total delay of approximately M×D p ; wherein the delay D p of each of the M passive delay elements is set by a corresponding one of M control inputs; and wherein each of the M control inputs receives a control signal comprising a global average tuning value added to one of M individual delay element tuning values.

Claim 27

The apparatus according to claim 21 , wherein the global average tuning value is determined from a tuning signal from the primary delay line.

Claim 28

The apparatus according to claim 22 , further comprising a memory cell receiving a signal from the primary DLL and storing the global average tuning.

Claim 29

The apparatus according to claim 22 , wherein each of the M individual delay element tuning values is stored in one of M memories.

Claim 30

The apparatus according to claim 21 , wherein the M individual delay element tuning values are determined based upon delay value variations in each of the M passive delay elements.

Claim 31

A delay locked loop circuit, comprising: a primary delay line having a plurality of N primary output taps; an N:1 multiplexer receiving signals from each of the N output taps and providing a multiplexer output signal, the multiplexer output being selected based upon a selected signal; a passive secondary delay circuit having an input receiving the multiplexer output signal, and having a plurality of M output taps; and wherein the select signal has least significant bits and most significant bits, and wherein taps in the primary delay line are selected by addressing a tap corresponding to the most significant bits and wherein a tap in the secondary delay circuit is selected by addressing a tap corresponding to the least significant bits.

Claim 32

A delay locked loop circuit, comprising: a primary delay line having a plurality of N primary output taps; an N:1 multiplexer receiving signals from each of the N output taps and providing a multiplexer output signal, the multiplexer output being selected based upon a selected signal; a passive secondary delay circuit having an input receiving the multiplexer output signal, and having a plurality of M output taps; and wherein the select signal has least significant bits and most significant bits, and wherein taps in the primary delay line are selected by addressing a tap corresponding to the most significant bits and wherein a tap in the secondary delay circuit is selected by addressing a tap corresponding to the least significant bits.

Claim 33

A delay locked loop circuit, comprising: a primary delay line having an input that receives a clock signal, having an output and having a plurality of N output taps from a plurality of delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×D; a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that is applied to the control input that sets the total delay to a delay that locks the delay locked loop; an N:1 multiplexer receiving signals from each of the N output taps and providing a multiplexer output signal under control of a select signal; a passive secondary delay circuit having an input receiving the multiplexer output signal, and having a plurality of M output taps at each of a plurality of M passive delay elements each having a delay D p the secondary delay circuit having a total delay of approximately M×D p that is set by a control signal, the control signal being determined by a tuning signal from the primary delay line that establishes a global average tuning; an output control circuit that selects one or more taps from the primary delay line and the secondary delay circuit as an output; a memory cell receiving the signal from the primary delay line and storing the global average tuning, and wherein the control signal to the passive secondary delay circuit is received as a fixed value of a global average tuning stored in the memory cell; and wherein the delay D p of each of the M passive delay elements is set by a corresponding one of M control inputs.

Claim 34

A delay locked loop circuit, comprising: a primary delay line having an input that receives a clock signal, having an output and having a plurality of N output taps from a plurality of delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×D; a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that is applied to the control input that sets the total delay to a delay that locks the delay locked loop; an N:1 multiplexer receiving signals from each of the N output taps and providing a multiplexer output signal under control of a select signal; a passive secondary delay circuit having an input receiving the multiplexer output signal, and having a plurality of M output taps at each of a plurality of M passive delay elements each having a delay D p the secondary delay circuit having a total delay of approximately M×D p that is set by a control signal, the control signal being determined by a tuning signal from the primary delay line that establishes a global average tuning; an output control circuit that selects one or more taps from the primary delay line and the secondary delay circuit as an output; a memory cell receiving the signal from the primary delay line and storing the global average tuning, and wherein the control signal to the passive secondary delay circuit is received as a fixed value of a global average tuning stored in the memory cell; and wherein the delay D p of each of the M passive delay elements is set by a corresponding one of M control inputs.

Claim 35

The apparatus according to claim 27 , wherein each of the M control inputs receives a control signal comprising a global average tuning value added to one of M individual delay element tuning values.

Claim 36

The apparatus according to claim 28 , wherein the global average tuning value is determined from a tuning signal from the primary delay line.

Claim 37

The apparatus according to claim 29 , further comprising a memory cell receiving a signal from the primary delay line and storing the global average tuning.

Claim 38

The apparatus according to claim 29 , wherein each of the M individual delay element tuning values is stored in one of M memories.

Claim 39

The apparatus according to claim 28 , wherein the M individual delay element tuning values are determined based upon delay value variations in each of the M passive delay elements.

Claim 40

A delay locked loop circuit, comprising: a primary delay line having an input that receives a clock signal, having an output and having a plurality of N output taps from a plurality of delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×D; a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that is applied to the control input that sets the total delay to a delay that locks the delay locked loop; an N:1 multiplexer receiving signals from each of the N output taps and providing a multiplexer output signal under control of a select signal; a passive secondary delay circuit having an input receiving the multiplexer output signal, and having a plurality of M output taps at each of a plurality of M passive delay elements each having a delay D p , the secondary delay circuit having a total delay of approximately M×D p ; an output control circuit that selects one or more taps from the primary delay line and the secondary delay circuit as an output; and wherein the output control circuit receives a digital frequency selection signal having least significant bits and most significant bits, and wherein the select signal comprises the most significant bits and wherein a tap in the secondary delay line is selected by addressing a tap corresponding to the least significant bits.

Claim 41

A delay locked loop circuit, comprising: a primary delay line having an input that receives a clock signal, having an output and having a plurality of N output taps from a plurality of delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×D; a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that is applied to the control input that sets the total delay to a delay that locks the delay locked loop; an N:1 multiplexer receiving signals from each of the N output taps and providing a multiplexer output signal under control of a select signal; a passive secondary delay circuit having an input receiving the multiplexer output signal, and having a plurality of M output taps at each of a plurality of M passive delay elements each having a delay D p , the secondary delay circuit having a total delay of approximately M×D p ; an output control circuit that selects one or more taps from the primary delay line and the secondary delay circuit as an output; and wherein the output control circuit receives a digital frequency selection signal having least significant bits and most significant bits, and wherein the select signal comprises the most significant bits and wherein a tap in the secondary delay line is selected by addressing a tap corresponding to the least significant bits.

Claim 42

A delay locked loop circuit, comprising: a primary delay line having an input that receives a clock signal, having an output and having a plurality of N output taps from a plurality of N delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×D; a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that sets the total delay to a delay that locks the delay locked loop circuit; an N:1 multiplexer receiving signals from each of the N output taps and providing a multiplexer output signal under control of a select signal; a secondary delay circuit having an input receiving the multiplexer output signal, and having a plurality of M output taps at each of a plurality of delay elements each having a delay D s , the secondary delay circuit having a total delay of M×D s , where M×D s is different than N×D; an output control circuit that selects one or more output taps from either the primary delay line or the secondary delay circuit as an output; and wherein the output control circuit selects taps based upon an algorithm that: computes a ratio K.C of the clock signal's frequency to a desired output frequency where C is a fractional part and K is an integer part of the ratio; identifies a sequence of taps constituting a repeating tap cycle at approximately equally spaced delay increments, wherein a j th tap address C j is defined by C j =C j−1 C.

Claim 43

A delay locked loop circuit, comprising: a primary delay line having an input that receives a clock signal, having an output and having a plurality of N output taps from a plurality of N delay elements, the primary delay line further having a control input that controls an amount of delay D of delay elements based upon a control signal applied thereto, the primary delay line having a total delay of N×D; a phase comparator that compares the phase of the primary delay line input with the primary delay line output and generates the control signal that sets the total delay to a delay that locks the delay locked loop circuit; an N:1 multiplexer receiving signals from each of the N output taps and providing a multiplexer output signal under control of a select signal; a secondary delay circuit having an input receiving the multiplexer output signal, and having a plurality of M output taps at each of a plurality of delay elements each having a delay D s , the secondary delay circuit having a total delay of M×D s , where M×D s is different than N×D; an output control circuit that selects one or more output taps from either the primary delay line or the secondary delay circuit as an output; and wherein the output control circuit selects taps based upon an algorithm that: computes a ratio K.C of the clock signal's frequency to a desired output frequency where C is a fractional part and K is an integer part of the ratio; identifies a sequence of taps constituting a repeating tap cycle at approximately equally spaced delay increments, wherein a j th tap address C j is defined by C j =C j−1 C.

Claim 44

The apparatus according to claim 34 , further comprising sequentially selecting identified taps to produce an output at time increments approximating K.C×N×D.

Claim 45

The apparatus according to claim 35 , wherein the output control circuit selects taps based upon an algorithm that interpolates fractional tap values by selecting integer tap values that vary as the tap cycle repeats.