US6353649B1
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US
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Time interpolating direct digital synthesizer
Assignee: Motorola Solutions Inc
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Filing: 2000-06-02
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Granted: 2002-03-05
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Expires: 2020-06-02
Abstract
Abstract A direct digital synthesizer ( 200 ) includes a first accumulator ( 202 ) that acts as the frequency accumulator in order to generate the desired average frequency. A second accumulator ( 204 ) acts to generate a phase correction at each overflow, with the input into the phase correction accumulator ( 204 ) being a function of the input frequency. The clock signal of the phase correction accumulator ( 204 ) is the overflow signal ( 208 ) of the frequency accumulator ( 202 ). With this configuration, the frequency accumulator ( 202 ) generates the timing, and the phase correction accumulator ( 204 ) generates the interpolation value. The use of the two accumulators ( 202, 204 ) as described, eliminates the need to use a multiplier in the design which is a high current consumption device.
Inventors
- 👤 David E. Bockleman
- 👤 Jui-Kuo Juan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 09:37
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; G06F1/00; G06F1/02; G06F1/025; H; H03; H03L; H03L7/00; H03L7/06; H03L7/16
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
78 words
A synthesizer comprising: a clock for providing a reference clock signal; a first accumulator having an input port for receiving a number representative of a desired output frequency, said first accumulator providing an overflow signal; and a second accumulator including an input clock port responsive to said overflow signal, and an input port for receiving a scaled phase correction increment, and an output port providing an output signal representative of a required delay for the reference clock signal.
Claim 2
Dependent Claim
78 words
A synthesizer comprising: a clock for providing a reference clock signal; a first accumulator having an input port for receiving a number representative of a desired output frequency, said first accumulator providing an overflow signal; and a second accumulator including an input clock port responsive to said overflow signal, and an input port for receiving a scaled phase correction increment, and an output port providing an output signal representative of a required delay for the reference clock signal.
Claim 3
Dependent Claim
24 words
A synthesizer as defined in claim 1 , further comprising: a variable delay responsive to said output signal for delaying the reference clock signal.
Claim 4
Dependent Claim
26 words
A synthesizer as defined in claim 1 , wherein said output signal delays the reference clock signal in proportion to the value of the output signal.
Claim 5
Dependent Claim
19 words
A synthesizer as defined in claim 2 , wherein said variable delay comprises a plurality of fixed delay elements.
Claim 6
Dependent Claim
18 words
A synthesizer as defined in claim 4 , wherein said plurality of fixed delay elements are cascaded together.
Claim 7
Dependent Claim
20 words
A synthesizer as defined in claim 1 , wherein said input port of the first accumulator receives a modulation signal.
Claim 8
Dependent Claim
137 words
A synthesizer comprising: a clock for providing a reference clock signal; a first accumulator having an input port for receiving a number representative of a desired output frequency, said first accumulator providing an overflow signal; a second accumulator including an input clock port responsive to said overflow signal, and an input port for receiving a scaled phase correction increment, and an output port providing an output signal representative of a required delay for the reference clock signal; and a variable delay responsive to said output signal for delaying the reference clock signal; wherein the scaled phase correction increment is equal to D(1-Fraction(C/N)), where C is equal to the capacity of the first accumulator, D is the number of taps in the variable delay, and N is a value representative of the desired output frequency for the synthesizer.
Claim 9
Dependent Claim
137 words
A synthesizer comprising: a clock for providing a reference clock signal; a first accumulator having an input port for receiving a number representative of a desired output frequency, said first accumulator providing an overflow signal; a second accumulator including an input clock port responsive to said overflow signal, and an input port for receiving a scaled phase correction increment, and an output port providing an output signal representative of a required delay for the reference clock signal; and a variable delay responsive to said output signal for delaying the reference clock signal; wherein the scaled phase correction increment is equal to D(1-Fraction(C/N)), where C is equal to the capacity of the first accumulator, D is the number of taps in the variable delay, and N is a value representative of the desired output frequency for the synthesizer.
Claim 10
Dependent Claim
144 words
A synthesizer comprising: a clock for providing a reference clock signal; a first accumulator having an input port for receiving a number representative of a desired output frequency, said first accumulator providing an overflow signal; a second accumulator including an input clock port responsive to said overflow signal, and an input port for receiving a scaled phase correction increment, and an output port providing an output signal representative of a required delay for the reference clock signal; and a phase correction control circuit for receiving the overflow signal from the first accumulator and the reference clock signal from the clock, the phase correction control circuit providing the overflow signal to the second accumulator when “N” is less than ½ of “C”, where “N” is a value representative of the desired output frequency for the synthesizer and “C” is the capacity of the first accumulator.
Claim 11
Dependent Claim
144 words
A synthesizer comprising: a clock for providing a reference clock signal; a first accumulator having an input port for receiving a number representative of a desired output frequency, said first accumulator providing an overflow signal; a second accumulator including an input clock port responsive to said overflow signal, and an input port for receiving a scaled phase correction increment, and an output port providing an output signal representative of a required delay for the reference clock signal; and a phase correction control circuit for receiving the overflow signal from the first accumulator and the reference clock signal from the clock, the phase correction control circuit providing the overflow signal to the second accumulator when “N” is less than ½ of “C”, where “N” is a value representative of the desired output frequency for the synthesizer and “C” is the capacity of the first accumulator.
Claim 12
Dependent Claim
148 words
A synthesizer comprising: a clock for providing a reference clock signal; a first accumulator having an input port for receiving a number representative of a desired output frequency, said first accumulator providing an overflow signal; a second accumulator including an input clock port responsive to said overflow signal, and an input port for receiving a scaled phase correction increment, and an output port providing an output signal representative of a required delay for the reference clock signal; and a phase correction control circuit for receiving the overflow signal from the first accumulator and the reference clock signal from the clock, the phase correction control circuit providing the reference clock signal to the second accumulator when “N” is equal to or greater than ½ of “C”, where “N” is a value representative of the desired output frequency for the synthesizer and “C” is the capacity of the first accumulator.
Claim 13
Dependent Claim
148 words
A synthesizer comprising: a clock for providing a reference clock signal; a first accumulator having an input port for receiving a number representative of a desired output frequency, said first accumulator providing an overflow signal; a second accumulator including an input clock port responsive to said overflow signal, and an input port for receiving a scaled phase correction increment, and an output port providing an output signal representative of a required delay for the reference clock signal; and a phase correction control circuit for receiving the overflow signal from the first accumulator and the reference clock signal from the clock, the phase correction control circuit providing the reference clock signal to the second accumulator when “N” is equal to or greater than ½ of “C”, where “N” is a value representative of the desired output frequency for the synthesizer and “C” is the capacity of the first accumulator.
Claim 14
Dependent Claim
158 words
A synthesizer comprising: a clock for providing a reference clock signal; a first accumulator having an input port for receiving a number representative of a desired output frequency, said first accumulator providing an overflow signal; a second accumulator including an input clock port responsive to said overflow signal, and an output port providing an output signal representative of a required delay for the reference clock signal, and an input port; and a digital-to-phase converter coupled to the second accumulator having a variable delay and a synthesizer output port; wherein the second accumulator receives at the input port a scaled phase correction increment equal to D(1-Fraction(C/N)), where C is equal to the capacity of the first accumulator, D is the number of taps in the variable delay, and N is a value representative of the desired output frequency for the synthesizer, and an output port providing an output signal representative of the required delay of the reference clock signal.
Claim 15
Dependent Claim
158 words
A synthesizer comprising: a clock for providing a reference clock signal; a first accumulator having an input port for receiving a number representative of a desired output frequency, said first accumulator providing an overflow signal; a second accumulator including an input clock port responsive to said overflow signal, and an output port providing an output signal representative of a required delay for the reference clock signal, and an input port; and a digital-to-phase converter coupled to the second accumulator having a variable delay and a synthesizer output port; wherein the second accumulator receives at the input port a scaled phase correction increment equal to D(1-Fraction(C/N)), where C is equal to the capacity of the first accumulator, D is the number of taps in the variable delay, and N is a value representative of the desired output frequency for the synthesizer, and an output port providing an output signal representative of the required delay of the reference clock signal.
Claim 16
Dependent Claim
18 words
A synthesizer as defined in claim 10 , wherein the digital-to-phase converter includes a delay lock loop (DLL).
Claim 17
Dependent Claim
21 words
A synthesizer as defined in claim 11 , wherein the DLL comprises a chain of inverters used as tunable delay elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-03-04 | 2005-09-03 | 2006-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-03-04 | 2009-09-03 | 2010-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-03-04 | 2013-09-03 | 2014-03-05 | $7700.00 | Window Closed / Lapsed |