Frequency synthesizer

Claim 2

A circuit, including one or more circuits for frequency synthesis, at least one of said circuits for frequency synthesis comprising: a first controlled oscillator which is digitally controlled and adapted to generate a signal representing a remainder, comprising: a clock generator; an accumulator circuit to which the signal from the clock generator is fed; and a control digit feed circuit for feeding to the accumulator circuit a signal representing a control digit; a phase-locked loop which is connected, via a combination circuit, to a carry output terminal of the accumulator circuit and which is provided with a phase detector, a low-pass filter incorporated in the phase-locked loop after the phase detector, and a second controlled oscillator incorporated in the phase-locked loop after the low pass filter and before the phase detector, wherein the carry output terminal is connected to the phase detector via said combination circuit; and a correction circuit for deriving a correction signal from the signal representing a remainder characterized in that an output terminal of the correction circuit is connected to said combination circuit which is connected to an input terminal of the phase detector.

Claim 3

Circuit as claimed in claim 1, characterized in that the output of the correction circuit is connected to a D/A-converter, and the output of the D/A-converter is also connected to an adder circuit (14a) incorporated in the PLL after the phase detector.

Claim 4

Circuit as claimed in claim 2, characterized in that the correction circuit comprises N accumulator circuits, wherein the first of said N accumulator circuits is adapted to receive said signal representing a remainder, and each of the remaining N accumulator circuits after the first is adapted to receive a remainder of the preceding accumulator circuit in the correction circuit and each of the N accumulator circuits is connected to a second adder circuit via a plurality of difference determining circuits equal to an order number of the accumulator circuit in the correction circuit minus 1.

Claim 5

Circuit as claimed in claim 3, characterized in that a divider circuit is arranged between the second controlled oscillator and the phase detector.

Claim 6

Circuit as claimed in claim 4, characterized by a cascade circuit of combinations of at least two of said first controlled oscillator and at least two of said phase-locked loop.

Claim 7

Circuit as claimed in claim 1, characterized in that the correction circuit is connected to at least one delay circuit incorporated in the PLL.

Claim 8

Circuit as claimed in claim 6, characterized in that at least one divider is arranged between the second controlled oscillator and the delay circuit and that the output terminal of the divider is directly connected to a clock terminal of the delay circuit.

Claim 9

Circuit as claimed in claim 7, characterized in that at least one modulo divider is arranged at the output terminal of the accumulator circuit and that a carry signal of the modulo divider is also fed to the correction circuit.

Claim 10

Circuit as claimed in claim 8, characterized in that the output terminal of the modulo divider is connected to a second second modulo divider and that the carry output signal of the modulo divider is fed to the phase detector of the PLL.

Claim 11

The circuit as claimed in claim 1, characterized in that a divider circuit is arranged between the second controlled oscillator and the phase detector.

Claim 12

The circuit as claimed in claim 1, characterized by a cascade circuit of combinations of at least two of said first controlled oscillator and at least two of said phase-locked loop.

Claim 13

Circuit for frequency synthesis, comprising: a first controlled oscillator which is digitally controlled and adapted to generate a signal representing a remainder, comprising: a clock generator; an accumulator circuit to which a signal from the clock generator is fed; and a control digit feed circuit for feeding to the accumulator circuit a signal representing a control digit; a phase-locked loop which is connected, via one or more delay circuits, to a carry output terminal of the accumulator circuit and which is provided with a phase detector, a low-pass filter incorporated in the phase-locked loop after the phase detector, and a second controlled oscillator incorporated in the phase-locked loop after the low-pass filter and before the phase detector, wherein the carry output terminal is connected to the phase detector via said one or more delay circuits; and a correction circuit for deriving a correction signal from the signal representing a remainder, comprising: N accumulator circuits, wherein the first of said N accumulator circuits is adapted to receive said signal representing a remainder, and each of the N accumulator circuits after the first is adapted to receive a remainder of the preceding accumulator circuit in the correction circuit, and each of the N accumulator circuits is connected to an adder circuit via a plurality of difference determining circuits equal to an order number of the accumulator circuit in the correction circuit minus 1; and a D/A converter connected to an output of said adder circuit; characterized in that an output terminal of the D/A converter of said correction circuit is connected to a second adder circuit (14a) incorporated in the PLL after the phase detector.

Claim 14

Circuit for frequency synthesis, comprising: a first controlled oscillator which is digitally controlled and adapted to generate a signal representing a remainder, comprising: a clock generator; an accumulator circuit to which a signal from the clock generator is fed; and a control digit feed circuit for feeding to the accumulator circuit a signal representing a control digit; a phase-locked loop which is connected, via one or more delay circuits, to a carry output terminal of the accumulator circuit and which is provided with a phase detector, a low-pass filter incorporated in the phase-locked loop after the phase detector, and a second controlled oscillator incorporated in the phase-locked loop after the low-pass filter and before the phase detector, wherein the carry output terminal is connected to the phase detector via said one or more delay circuits; and a correction circuit for deriving a correction signal from the signal representing a remainder, comprising: N accumulator circuits, wherein the first of said N accumulator circuits is adapted to receive said signal representing a remainder, and each of the N accumulator circuits after the first is adapted to receive a remainder of the preceding accumulator circuit in the correction circuit, and each of the N accumulator circuits is connected to an adder circuit via a plurality of difference determining circuits equal to an order number of the accumulator circuit in the correction circuit minus 1; and a D/A converter connected to an output of said adder circuit; characterized in that an output terminal of the D/A converter of said correction circuit is connected to a second adder circuit (14a) incorporated in the PLL after the phase detector.