US4746880A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Number controlled modulated oscillator
Assignee: DIGITAL RF SOLUTIONS Corp A CORP OF CA
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Filing: 1987-02-06
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Granted: 1988-05-24
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Expires: 2007-02-06
Abstract
Abstract Disclosed is a number controlled, modulated, oscillator employing a modulation selector for receiving a digital number for use for frequency modulation or for phase modulation, a tuning network for receiving another digital number in a variety of forms, and a frequency modulator for adding the value of the modulation selector number to that of the tuning network number. Also, the oscillator employs a phase accumulator for adding the value of the frequency modulator sum to that of a number already stored in the phase accumulator and replacing the stored number with the phase accumulator sum at each of a series of times specified by a clocking signal. Further, the oscillator employs a phase modulator for adding the value of the number stored in the phase accumulator to that of the modulation selector number and an output selector developing the 1's compliment of the phase modulator sum and for selecting either the phase modulator sum or the complimented number. Finally, the oscillator employs a waveform map for storing a quantity of amplitude numbers and for retrieving the number stored at the location addressed by the (modulated) phase accumulator selected number, a digital multiplier for receiving a number and for multiplying the value of the received number by that of the retrieved number, and a digital-to-analog converter for developing a signal having, as an amplitude, the multiplier product.
Inventors
- 👤 Earl W. McCune, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:24
CPC Classifications
H; H03; H03C; H03C3/00; H03C3/02; H03C3/09; G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0321; G06F1/0328; G06F1/0335
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
404 words
An oscillator comprising in combination: a frequency modulator including an adder having a first set of addend inputs for receiving signals representing a first digital number, a second set of addend inputs for receiving signals representing a second digital number, and a set of outputs at which said frequency modulator adder develops signals representing the sum of the value of said first and said second numbers; a phase accumulator including an adder having a first set of addend inputs connected to said set of outputs of said frequency modulator adder for receiving said frequency modulator adder developed sum signals, a second set of addend inputs for receiving signals representing a stored number, and a set of outputs at which said phase accumulator adder develops signals representing the sum of the value of said frequency modulator adder developed sum and said stored number and a latch having a set of data inputs connected to said set of outputs of said phase accumulator adder for receiving said phase accumulator adder developed sum signals, a clock input for connection to receive an externally generated clocking signal, and a set of data outputs connected to said second set of phase accumulator adder addend inputs, said phase accumulator latch for latching the state of said phase accumulator adder developed sum signals at each of a series of times delineated by said clocking signal to develop said stored number signals; a phase modulator including an adder having a first set of addend inputs for receiving signals representing a third digital number, a second set of addend inputs connected to said set of outputs of said phase accumulator latch for receiving said stored number signals, and a set of outputs at which said phase modulator adder develops signals representing the sum of the value of said third number and the value of said stored number; and a modulation selector for connection to receive externally generated signals representing a fourth digital number, for connection to receive an externally generated selecting signal, connected to said first set of frequency modulator adder addend inputs, and connected to said first set of phase modulator adder addend inputs, said modulation selector for developing said first digital number signals and said third digital number signals so that the value of one of said first and said third numbers is the same as the value of said fourth number as determined by the state of said selecting signal.
Claim 2
Dependent Claim
404 words
An oscillator comprising in combination: a frequency modulator including an adder having a first set of addend inputs for receiving signals representing a first digital number, a second set of addend inputs for receiving signals representing a second digital number, and a set of outputs at which said frequency modulator adder develops signals representing the sum of the value of said first and said second numbers; a phase accumulator including an adder having a first set of addend inputs connected to said set of outputs of said frequency modulator adder for receiving said frequency modulator adder developed sum signals, a second set of addend inputs for receiving signals representing a stored number, and a set of outputs at which said phase accumulator adder develops signals representing the sum of the value of said frequency modulator adder developed sum and said stored number and a latch having a set of data inputs connected to said set of outputs of said phase accumulator adder for receiving said phase accumulator adder developed sum signals, a clock input for connection to receive an externally generated clocking signal, and a set of data outputs connected to said second set of phase accumulator adder addend inputs, said phase accumulator latch for latching the state of said phase accumulator adder developed sum signals at each of a series of times delineated by said clocking signal to develop said stored number signals; a phase modulator including an adder having a first set of addend inputs for receiving signals representing a third digital number, a second set of addend inputs connected to said set of outputs of said phase accumulator latch for receiving said stored number signals, and a set of outputs at which said phase modulator adder develops signals representing the sum of the value of said third number and the value of said stored number; and a modulation selector for connection to receive externally generated signals representing a fourth digital number, for connection to receive an externally generated selecting signal, connected to said first set of frequency modulator adder addend inputs, and connected to said first set of phase modulator adder addend inputs, said modulation selector for developing said first digital number signals and said third digital number signals so that the value of one of said first and said third numbers is the same as the value of said fourth number as determined by the state of said selecting signal.
Claim 3
Dependent Claim
53 words
An oscillator as recited in claim 1 further comprising a tuning network connected to said second set of frequency modulator adder addend inputs, said tuning network including means for storing said second digital number and for developing said second digital number signals and means for updating a selected portion of said stored number.
Claim 4
Dependent Claim
63 words
An oscillator as recited in claim 1 further comprising a waveform map coupled to receive signals derived from said phase modulator adder sum signals, said waveform map including a predetermined number of storage locations each storing a number, said waveform map for developing signals representing the number stored at the location addressed by said signals derived from said phase modulator adder sum signals.
Claim 5
Dependent Claim
68 words
An oscillator as recited in claim 3 further comprising a digital multiplier including a first set of inputs connected to said waveform map for receiving said stored number signals a second set of inputs for connection to receive externally developed signals representing a fifth number, said digital multiplier for developing signals representing the product of the value of said stored number and the value of said fifth number.
Claim 6
Dependent Claim
24 words
An oscillator as recited in claim 3 further comprising a digital-to-analog converter coupled to receive signals derived from said waveform map stored number signals.
Claim 7
Dependent Claim
378 words
An oscillator comprising in combination: a frequency modulator including an adder having a first set of addend inputs for receiving signals representing a first digital number, a second set of addend inputs for receiving signals representing a second digital number, and a set of outputs at which said frequency modulator adder develops signals representing the sum of the value of said first and said second numbers; a phase accumulator including an adder having a first set of addend inputs connected to said set of outputs of said frequency modulator adder for receiving said frequency modulator adder developed sum signals, a second set of addend inputs for receiving signals representing a stored number, and a set of outputs at which said phase accumulator adder develops signals representing the sum of the value of said frequency modulator adder developed sum and said stored number and a latch having a set of data inputs connected to said set of outputs of said phase accumulator adder for receiving said phase accumulator adder developed sum signals, a clock input for connection to receive an externally generated clocking signal, and a set of data outputs connected to said second set of phase accumulator adder addend inputs, said phase accumulator latch for latching the state of said phase accumulator adder developed sum signals at each of a series of times delineated by said clocking signal to develop said stored number signals; a phase modulator including an adder having a first set of addend inputs for receiving signals representing a third digital number, a second set of addend inputs connected to said set of outputs of said phase accumulator latch for receiving said stored number signals, and a set of outputs at which said phase modulator adder develops signals representing the sum of the value of said third number and the value of said stored number; and an output selector connected to said set of phase modulator adder outputs for receiving said phase modulator adder developed sum signals, said output selector including means for developing a number the value of which is the 1's compliment of at least a portion of said phase modulator adder sum and means for developing signals representing a selected one of said phase modulator adder sum and said 1's compliment number.
Claim 8
Dependent Claim
378 words
An oscillator comprising in combination: a frequency modulator including an adder having a first set of addend inputs for receiving signals representing a first digital number, a second set of addend inputs for receiving signals representing a second digital number, and a set of outputs at which said frequency modulator adder develops signals representing the sum of the value of said first and said second numbers; a phase accumulator including an adder having a first set of addend inputs connected to said set of outputs of said frequency modulator adder for receiving said frequency modulator adder developed sum signals, a second set of addend inputs for receiving signals representing a stored number, and a set of outputs at which said phase accumulator adder develops signals representing the sum of the value of said frequency modulator adder developed sum and said stored number and a latch having a set of data inputs connected to said set of outputs of said phase accumulator adder for receiving said phase accumulator adder developed sum signals, a clock input for connection to receive an externally generated clocking signal, and a set of data outputs connected to said second set of phase accumulator adder addend inputs, said phase accumulator latch for latching the state of said phase accumulator adder developed sum signals at each of a series of times delineated by said clocking signal to develop said stored number signals; a phase modulator including an adder having a first set of addend inputs for receiving signals representing a third digital number, a second set of addend inputs connected to said set of outputs of said phase accumulator latch for receiving said stored number signals, and a set of outputs at which said phase modulator adder develops signals representing the sum of the value of said third number and the value of said stored number; and an output selector connected to said set of phase modulator adder outputs for receiving said phase modulator adder developed sum signals, said output selector including means for developing a number the value of which is the 1's compliment of at least a portion of said phase modulator adder sum and means for developing signals representing a selected one of said phase modulator adder sum and said 1's compliment number.
Claim 9
Dependent Claim
104 words
An oscillator as recited in claim 6 further comprising a modulation selector for connection to receive externally generated signals representing a fourth digital number, for connection to receive an externally generated selecting signal, connected to said first set of frequency modulator adder addend inputs, and connected to said first set of phase modulator adder addend inputs, said modulation selector for developing said first digital number signals and said third digital number signals so that the value of one of said first and said third numbers is the same as the value of said fourth number as determined by the state of said selecting signal.
Claim 10
Dependent Claim
53 words
An oscillator as recited in claim 6 further comprising a tuning network connected to said second set of frequency modulator adder addend inputs, said tuning network including means for storing said second digital number and for developing said second digital number signals and means for updating a selected portion of said stored number.
Claim 11
Dependent Claim
63 words
An oscillator as recited in claim 6 further comprising a waveform map coupled to receive signals derived from said phase modulator adder sum signals, said waveform map including a predetermined number of storage locations each storing a number, said waveform map for developing signals representing the number stored at the location addressed by said signals derived from said phase modulator adder sum signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-24 | 1991-11-23 | 1992-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-24 | 1995-11-23 | 1996-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-24 | 1999-11-23 | 2000-05-24 | $7700.00 | Window Closed / Lapsed |