US4003003A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multichannel digital synthesizer and modulator
Assignee: Individual
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Filing: 1975-11-18
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Granted: 1977-01-11
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Expires: 1995-11-18
Abstract
Abstract Apparatus for generating a coherent multichannel signal. The signal for each channel can be independently phase, frequency and amplitude modulated. The coherent multichannel signal is locked to a reference signal. A frequency generator establishes, at each output sample time, the phase information for each channel. A waveshape section converts the phase information into amplitude information to generate the desired waveforms. A multiplier amplitude modulates the generated waveforms which are converted into an analog voltage and fed to a low pass filter for smoothing the output and eliminating undesired high frequencies.
Inventors
- 👤 Allen L. Heaberlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:11
CPC Classifications
H; H04; H04J; H04J1/00; H04J1/02; H04J1/06; G; G10; G10H; G10H7/00; G10H7/02; G10H7/04; H03; H03C; H03C5/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
174 words
Apparatus for generating a coherent multichannel signal comprising: a. a reference frequency source for providing signals at a predetermined reference frequency; b. counter means coupled to said reference frequency source for consecutively sequencing through said reference signals; c. increment circuit means having a first input coupled to said counter means and having a second input coupled to a frequency modulation source for generating an increment signal representing the frequency for each of the channel numbers; d. phase information circuit means coupled to said increment circuit means for converting each of said increment signals into an output signal representing the phase information at each sampling point for each channel; e. waveshape circuit means coupled to said phase information circuit means and being responsive to each of said output signals and its associated phase information for converting said phase information into digital amplitude information signals; f. and digital-to-analog converter means coupled to said waveshape circuit means for converting said digital signals into an analog signal that is the sum of said predetermined number of consecutive signals.
Claim 2
Dependent Claim
174 words
Apparatus for generating a coherent multichannel signal comprising: a. a reference frequency source for providing signals at a predetermined reference frequency; b. counter means coupled to said reference frequency source for consecutively sequencing through said reference signals; c. increment circuit means having a first input coupled to said counter means and having a second input coupled to a frequency modulation source for generating an increment signal representing the frequency for each of the channel numbers; d. phase information circuit means coupled to said increment circuit means for converting each of said increment signals into an output signal representing the phase information at each sampling point for each channel; e. waveshape circuit means coupled to said phase information circuit means and being responsive to each of said output signals and its associated phase information for converting said phase information into digital amplitude information signals; f. and digital-to-analog converter means coupled to said waveshape circuit means for converting said digital signals into an analog signal that is the sum of said predetermined number of consecutive signals.
Claim 3
Dependent Claim
17 words
The apparatus of claim 1 wherein said increment circuit means is a frequency read only memory circuit.
Claim 4
Dependent Claim
81 words
The apparatus of claim 1 wherein said phase information circuit means includes: a. a first circuit means coupled to said increment circuit means for generating phase information corresponding to an output sample rate that is slower than the frequency of said reference source; and b. second circuit means coupled to said increment circuit means and to said first circuit means for generating phase information corresponding to an output sample rate that is the same as the frequency of said reference source.
Claim 5
Dependent Claim
106 words
The apparatus of claim 3 wherein said first circuit means includes: a. shift circuit means for adjustably shifting the increment output to increase the increment number by a predetermined value, K; b. first adder circuit means having a first input coupled to said shift circuit means, a second input and an output; c. shift register means having a first input coupled to the output of said first adder means and having a second input coupled to a clocking source of the same frequency as said counter circuit means and having an output, the output being coupled to the second input of said first adder circuit means.
Claim 6
Dependent Claim
111 words
The apparatus of claim 4 wherein said second circuit means includes: a. a multiplexer circuit means having a first input coupled to the output of said shift register means, a second input and an output; b. second adder circuit means having a first input coupled to the output of said increment circuit means, a second input coupled to the output of said multiplexer circuit means and an output, c. a first buffer register means having a first input coupled to the output of said second adder circuit means, a second input coupled to a clocking source of a predetermined frequency and an output coupled to the second input of said multiplexer.
Claim 7
Dependent Claim
89 words
The apparatus of claim 1 wherein said waveshape circuit means includes: a. first circuit means having a phase information input, a phase modulation input, a channel number input and an amplitude modulation input for generating a signal representing the amplitude for each of the output samples for each channel; b. second circuit means having a first input coupled to said first circuit means for adding all the sampled values for all channels corresponding to the same sample time and buffers the summed signal to provide a digital output signal.
Claim 8
Dependent Claim
100 words
The apparatus of claim 6 wherein said first circuit means includes: a. a third adder circuit means having a first input coupled to the output of said phase information circuit means, a phase modulation input and an output; b. a waveshape read only memory having an input coupled to the output of said third adder circuit means, a channel number input coupled to the output of said counter means and an output; c. a multiplier circuit means having a first input coupled to the output of said memory, a second input adapted to receive amplitude modulation signals and an output.
Claim 9
Dependent Claim
152 words
The apparatus of claim 7 wherein said second circuit means includes: a. a fourth adder circuit means having a first input coupled to the output of said multiplier circuit means, a second input and an output; b. a register having a first input coupled to the output of said fourth adder circuit means, a second input coupled to a clocking source of the same frequency as the clocking source for said phase information circuit means, and an output connected to the second input of said fourth adder; c. second buffer register means having a first input coupled to the output of said register means, a second input coupled to a variable clocking source and an output; d. a third buffer register having an input coupled to the output of said second buffer register, a second input coupled to a clocking source of the same frequency as said reference frequency and an output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-11 | 1980-07-12 | 1981-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-11 | 1984-07-12 | 1985-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-11 | 1988-07-12 | 1989-01-11 | $7700.00 | Window Closed / Lapsed |