Frequency modulation system for transmitting binary information

Claim 3

a filter for eliminating the discontinuities in the output signal of the digital to analog converter to produce a sinusoidal output signal; means for applying a series of input pulses to said converting circuIt; and means for varying the frequency of the input pulses applied to said converting circuit to vary the frequency of the sinusoidal output signal and produce a frequency modulated sinusoidal signal.

Claim 4

a filter for eliminating the discontinuities in the output signal of the digital to analog converter to produce a sinusoidal output signal; means for applying a series of input pulses to said converting circuIt; and means for varying the frequency of the input pulses applied to said converting circuit to vary the frequency of the sinusoidal output signal and produce a frequency modulated sinusoidal signal.

Claim 5

The system of claim 1, wherein: said means for applying a series of input pulses to said converting circuit includes a source for producing pulses at a predetermined frequency, and a frequency divider connected to said source for producing a series of pulses at a frequency which is less than the predetermined frequency; and said means for varying the frequency of the input pulses to said converting circuit comprises a frequency selecting circuit connected to said frequency divider for controlling the operation of said frequency divider to determine the frequency of the pulses produced at the output of said frequency divider.

Claim 6

a filter for eliminating the discontinuities in the output signal of the digital to analog converter to produce a sinusoidal output signal.

Claim 7

a filter for eliminating the discontinuities in the output signal of the digital to analog converter to produce a sinusoidal output signal.

Claim 8

The system of claim 2, wherein the digital to analog converter comprises: a counting circuit having a plurality of binary counting stages which are turned on and then turned off in a predetermined sequence in response to input pulses applied to the counting circuit; and means for combining the output signals produced by said binary counting stages to provide a signal consisting of a series of incremental voltage changes corresponding to the changes in voltage which occur in a sinusoidal signal.

Claim 9

The system of claim 3, wherein the means for combining the output signals produced by the binary counting stages comprises: a resistance summing network including a plurality of weighted resistances connected to output terminals of said counting stages and to a common output terminal, said resistance summing network producing an output signal at said common output terminal consisting of a series of incremental voltage changes corresponding to the changes in voltage which occur in the sinusoidal signal.

Claim 10

The system of claim 4, which includes: a resistance bridge having a terminal connected to the common output terminal of said resistance summing network.

Claim 11

The system of claim 1, wherein the digital to analog converter includes: a counting circuit having a plurality of binary counting stages operable in a predetermined sequence in which the binary stages are turned on one at a time until all of the stages are turned on, and then the binary stages are turned off one at a time until all the stages are turned off in response to input pulses applied to the counting circuit; and means for combining the output signals produced by the binary counting stages to provide a signal consisting of a series of incremental voltage changes corresponding to the changes in voltage which occur in a sinusoidal signal.

Claim 12

The system of claim 6, wherein the means for combining the output signals produced by the binary counting stages comprises: a resistance summing network including a plurality of weighted resistances connected to the outputs of the binary counting stages; said weighted resistances being weighted so as to produce incremental voltage changes at said common terminal corresponding to changes in voltage which occur in a sinusoidal signal in response to the output signals produced by the binary stages of said counting circuit. a frequency selecting circuit for controlling the operation of said frequency divider in response to a binary input signal to vary the frequency of the output pulses produced by said frequency divider to obtain pulses which occur at a first or second frequency; and a converting circuit connected to the output of said frequency divider for transforming the series of output pulses from the frequency divider into a sinusoidal signal having a frequency corresponding to the frequency of the output pulses to transmit the binary input signal in the form of a frequency modulated sinusoidal signal, said converting circuit comprising

Claim 15

The system of claim 8, wherein: said frequency divider includes a plurality of flip-flops arranged in a series; and said frequency selecting circuit interconnects at least two of the flip-flops of said frequency divider for selectively altering the operating sequence of the flip-flops of said frequency divider to change the frequency of the output pulses produced by the frequency divider.

Claim 16

The system of claim 9, wherein the frequency selecting circuit comprises: a set of gates responsive to a binary input signal to the system and to the output signals of one of the flip-flops of said frequency divider and having an output terminal connected to the clock input terminal of the next adjacent flip-flop of the frequency divider for altering the operating sequence of the flip-flops in response to the binary input signal.

Claim 17

The system of claim 9, wherein the frequency selecting circuit comprises: a binary input terminal for receiving binary input signals; an inverter having an input terminal connected to said binary input terminal and an output terminal; an OR gate having a pair of input terminals and an output terminal; a first NOR gate having an input terminal connected to said binary input terminal and another input terminal connected to an output terminal of one of the flip-flops of said frequency divider, said first NOR gate also having an output terminal connected to one of the input terminals of said OR gate; and a second NOR gate having an input terminal connected to the output terminal of said inverter and another input terminal connected to the other output terminal of that flip-flop, said second NOR gate also having an output terminal connected to the other input terminal of said OR gate; said output terminal of said OR gate being connected to the clock input terminal of the next adjacent flip-flop of said frequency divider.

Claim 18

The system of claim 9, wherein the frequency selecting circuit comprises: a first set of gates responsive to a binary input signal to the system and to the output signals of a first one of the flip-flops of said frequency divider and having an output terminal connected to the clock input terminal of the flip-flop of the frequency divider next adjacent to that first flip-flop for altering the operating sequence of the flip-flops in response to the binary input signal; and a second set of gates responsive to the binary input signal to the system and to the output signals of a second one of the flip-flops of said frequency divider and having an output terminal connected to the clock input terminal of the flip-flop of the frequency divider next adjacent to that second flip-flop for altering the operating sequence of the flip-flops in response to the binary input signal.

Claim 19

The system of claim 9, wherein the frequency selecting circuit comprises: a binary input terminal for receiving binary input signals; an inverter having an input terminal connected to said binary input terminal and an output terminal; a first set of gates comprising: a. a first OR gate having a pair of input terminals and an output terminal; b. a first NOR gate having an input terminal connected to said binary input terminal and another input terminal connected to an output terminal of a first one of the flip-flops of said frequency divider, said first NOR gate also having an output terminal connected to one oF the input terminals of said first OR gate; and c. a second NOR gate having an input terminal connected to the output terminal of said inverter and another input terminal connected to the other output terminal of that first flip-flop, said second NOR gate also having an output terminal connected to the other input terminal of said first OR gate; d. said output terminal of said first OR gate being connected to the clock input terminal of the flip-flop of said frequency divider next adjacent to that first flip-flop; and a second set of gates comprising: a. a second OR gate having a pair of input terminals and an output terminal; b. a third NOR gate having an input terminal connected to said binary input terminal and another input terminal connected to an output terminal of a second one of the flip-flops of said frequency divider, said third NOR gate also having an output terminal connected to one of the input terminals of said second OR gate; and c. a fourth NOR gate having an input terminal connected to the output terminal of said inverter and another input terminal connected to the other output terminal of that second flip-flop, said fourth NOR gate also having an output terminal connected to the other input terminal of said second OR gate; d. said output terminal of said second OR gate being connected to the clock input terminal of the flip-flop of said frequency divider next adjacent to that second flip-flop.