US5469479A
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Digital chirp synthesizer
Assignee: Texas Instruments Inc
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Filing: 1992-02-27
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Granted: 1995-11-21
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Expires: 2012-02-27
Abstract
Abstract A monolithic digital chirp synthesizer (DCS) chip using GaAs/AlGaAs HI 2 L technology. The 6500 HBT gate DCS chip is capable of producing linear frequency modulated (chirp) waveforms or single frequency waveforms. The major components of the DCS are two pipelined accumulators, a sine ROM, a cosine ROM and two digital to analog converters.
Inventors
- 👤 Christopher T.-M. Chang
- 👤 William A. White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:54
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/02; G01S7/28; G01S7/282; G01S13/00; G01S13/02; G01S13/06; G01S13/08; G01S13/10; G01S13/26; G01S13/28; G01S13/282; G01S13/32; G01S13/34
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
144 words
A direct digital chirp synthesizer for synthesizing a carrier frequency which is increased linearly for the duration of a pulse code, which comprises: (a) a rate register for receiving and storing an input signal; (b) a first digital accumulator for first adding said input signal stored in said rate register to a signal then stored in said first accumulator to provide and store a first new sum signal in said first accumulator in response to said first adding; (c) a second digital accumulator for second adding said first new sum signal to a signal then stored in said second accumulator to provide and store a second new sum signal in said second accumulator in response to said second adding; and (d) a function generator responsive to said second new sum signal to generate an analog function signal corresponding to said second new sum signal.
Claim 2
Dependent Claim
144 words
A direct digital chirp synthesizer for synthesizing a carrier frequency which is increased linearly for the duration of a pulse code, which comprises: (a) a rate register for receiving and storing an input signal; (b) a first digital accumulator for first adding said input signal stored in said rate register to a signal then stored in said first accumulator to provide and store a first new sum signal in said first accumulator in response to said first adding; (c) a second digital accumulator for second adding said first new sum signal to a signal then stored in said second accumulator to provide and store a second new sum signal in said second accumulator in response to said second adding; and (d) a function generator responsive to said second new sum signal to generate an analog function signal corresponding to said second new sum signal.
Claim 3
Dependent Claim
48 words
The synthesizer as set forth in claim 1 wherein said function generator is at least one of a sine wave ROM and a cosine wave ROM for generating a signal representing a sine wave and a cosine wave having a frequency related to said second new sum signal.
Claim 4
Dependent Claim
65 words
The synthesizer as set forth in claim 2 wherein said first accumulator comprises a first adder having a first input, a second input and a first output, said first output coupled to a first register, the output of said first register being coupled to said first input of said first adder and said rate register being coupled to said second input of said first adder.
Claim 5
Dependent Claim
65 words
The synthesizer as set forth in claim 3 wherein said second accumulator comprises a second adder having a third input, a fourth input and a second output, said second output coupled to a second register, the output of said second register being coupled to said third input of said second adder and said first output being coupled to said fourth input of said second adder.
Claim 6
Dependent Claim
29 words
The synthesizer as set forth in claim 4 wherein said rate register, said first and second accumulators and said function generator are all disposed on a single semiconductor chip.
Claim 7
Dependent Claim
29 words
The synthesizer as set forth in claim 3 wherein said rate register, said first and second accumulators and said function generator are all disposed on a single semiconductor chip.
Claim 8
Dependent Claim
64 words
The synthesizer as set forth in claim 2 wherein said second accumulator comprises a second adder having a third input, a fourth input and a second output, said second output coupled to a second register, the output of said second register being coupled to said third input of said second adder and said first output being,coupled to said fourth input of said second adder.
Claim 9
Dependent Claim
29 words
The synthesizer as set forth in claim 7 wherein said rate register, said first and second accumulators and said function generator are all disposed on a single semiconductor chip.
Claim 10
Dependent Claim
29 words
The synthesizer as set forth in claim 2 wherein said rate register, said first and second accumulators and said function generator are all disposed on a single semiconductor chip.
Claim 11
Dependent Claim
65 words
The synthesizer as set forth in claim 1 wherein said first accumulator comprises a first adder having a first input, a second input and a first output, said first output coupled to a first register, the output of said first register being coupled to said first input of said first adder and said rate register being coupled to said second input of said first adder.
Claim 12
Dependent Claim
65 words
The synthesizer as set forth in claim 10 wherein said second accumulator comprises a second adder having a third input, a fourth input and a second output, said second output coupled to a second register, the output of said second register being coupled to said third input of said second adder and said first output being coupled to said fourth input of said second adder.
Claim 13
Dependent Claim
29 words
The synthesizer as set forth in claim 11 wherein said rate register, said first and second accumulators and said function generator are all disposed on a single semiconductor chip.
Claim 14
Dependent Claim
29 words
The synthesizer as set forth in claim 10 wherein said rate register, said first and second accumulators and said function generator are all disposed on a single semiconductor chip.
Claim 15
Dependent Claim
65 words
The synthesizer as set forth in claim 1 wherein said second accumulator comprises a second adder having a third input, a fourth input and a second output, said second output coupled to a second register, the output of said second register being coupled to said third input of said second adder and said first output being coupled to said fourth input of said second adder.
Claim 16
Dependent Claim
29 words
The synthesizer as set forth in claim 14 wherein said rate register, said first and second accumulators and said function generator are all disposed on a single semiconductor chip.
Claim 17
Dependent Claim
29 words
The synthesizer as set forth in claim 1 wherein said rate register, said first and second accumulators and said function generator are all disposed on a single semiconductor chip.
Claim 18
Dependent Claim
33 words
The synthesizer of claim 1 wherein said function generator comprises means responsive to said second new sum signal to provide a representation of a trigonometric function corresponding to said second new sum signal.
Claim 19
Dependent Claim
33 words
The synthesizer of claim 17 wherein said representation of said trigonometric function is a digital representation thereof, further including a digital to analog converter for converting said digital representation to an analog representation.
Claim 20
Dependent Claim
35 words
The synthesizer as set forth in claim 18 wherein said rate register, said first and second accumulators and said means responsive to said second new sum signal are all disposed on a single semiconductor chip.
Claim 21
Dependent Claim
35 words
The synthesizer as set forth in claim 17 wherein said rate register, said first and second accumulators and said means responsive to said second new sum signal are all disposed on a single semiconductor chip.
Claim 22
Dependent Claim
105 words
A direct digital chirp synthesizer for synthesizing a carrier frequency which is increased linearly for the duration of a pulse code, which comprises: (a) a single semiconductor chip including thereon: (i) a rate register for receiving a digital input signal; (ii) accumulator means for adding the received digital input signal to a previously stored digital sum signal then stored in said accumulator means to provide and store in said accumulator means a later digital sum signal responsive to said adding; and (iii) a function generator responsive to said later digital sum signal to generate an analog function signal corresponding to said later digital sum signal.
Claim 23
Dependent Claim
105 words
A direct digital chirp synthesizer for synthesizing a carrier frequency which is increased linearly for the duration of a pulse code, which comprises: (a) a single semiconductor chip including thereon: (i) a rate register for receiving a digital input signal; (ii) accumulator means for adding the received digital input signal to a previously stored digital sum signal then stored in said accumulator means to provide and store in said accumulator means a later digital sum signal responsive to said adding; and (iii) a function generator responsive to said later digital sum signal to generate an analog function signal corresponding to said later digital sum signal.
Claim 24
Dependent Claim
97 words
The synthesizer of claim 21 wherein said accumulator means comprises a first accumulator element storing a prior first digital sum signal and adding said received digital input signal to said prior first digital sum signal to provide a later first digital sum signal and a second accumulator element for adding said later first digital sum signal to a prior second digital sum signal to provide a later second digital sum signal and storing said later second digital sum signal in said second accumulator element, said function generator being responsive to said later second later digital sum signal.
Claim 25
Dependent Claim
50 words
The synthesizer of claim 22 wherein said function generator comprises at least one of a sine ROM or a cosine ROM for generating a digital signal of at least one of sine coefficients or cosine coefficients corresponding to said later second digital sum signal stored in said second accumulator element.
Claim 26
Dependent Claim
34 words
The synthesizer of claim 23 wherein said function generator further includes a digital to analog converter to convert said digital signal corresponding to said later second digital sum signal to a corresponding analog signal.
Claim 27
Dependent Claim
43 words
The synthesizer of claim 21 wherein said function generator comprises at least one of a sine ROM or a cosine ROM for generating a digital signal of at least one of sine coefficients or cosine coefficients corresponding to said later digital sum signal.
Claim 28
Dependent Claim
33 words
The synthesizer of claim 25 wherein said function generator further includes a digital to analog converter to convert said digital signal corresponding to said later digital sum signal to a corresponding analog signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |