US6492851B2
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Digital phase control circuit
Assignee: Renesas Electronics Corp
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Filing: 2001-03-29
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Granted: 2002-12-10
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Expires: 2021-03-29
Abstract
Abstract The digital phase control circuit of the present invention is provided with: voltage-controlled delay line VCDL1 in which differential buffers (G1-G10) having a propagation delay time of 160 ps are concatenated in a plurality of stages; voltage-controlled delay line (VCDL2) in which differential buffers (H1-H8) having a propagation delay time of 200 ps are concatenated in a plurality of stages; selector (S2) that extracts a clock signal from any stage of voltage-controlled delay line (VCDL1) and outputs to the first stage of voltage-controlled delay line (VCDL2); and selector S3 that extracts and outputs a clock signal from any stage of voltage-controlled delay line (VCDL2). This digital phase control circuit (10) feedback-controls voltage-controlled delay line (VCDL1) and voltage-controlled delay line (VCDL2) by delay locked loops (DLL1) and (DLL2), controls the phases of clock signals with the difference 40 ps between 160 ps and 200 ps as the resolution; and therefore is a power-saving, compact, and high-resolution digital phase control circuit that suppresses increase in power consumption and increase in the area occupied by circuits to a minimum.
Inventors
- 👤 Seiichi Watarai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:16
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/07; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/085; H03L7/089; H03L7/0891
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
253 words
A digital phase control circuit that outputs one or more clock signals in which phase is controlled at a prescribed resolution with respect to received reference clock signals, comprising: a first delay locked loop that is feedback-controlled and that contains a first voltage-controlled delay line comprising delay buffers having a first type of propagation delay time concatenated in h stages and that receives a selected one of said reference clock signals; a second delay locked loop that is feedback-controlled and that contains i second voltage-controlled delay lines that are each connected to one of a respective output of i stages of outputs of said first voltage-controlled delay line and said selected at least one of said reference clock signals, each said second voltage-controlled delay line comprising delay buffers having a second type of propagation delay time concatenated in j stages; a third delay locked loop that is feedback-controlled and that contains a third voltage-controlled delay line that is composed of delay buffers having said second type of propagation delay time concatenated in k stages; and a selector that switches a clock signal from one of selected ones of stages of said first voltage-controlled delay line and said second voltage-controlled delay line to be an input into said third voltage-controlled delay line wherein, a delay control voltage or current for maintaining resolution that is generated by said third delay locked loop that feedback-controls said third voltage-controlled delay line is supplied to each of the delay buffers of each of said second voltage-controlled delay lines.
Claim 2
Dependent Claim
253 words
A digital phase control circuit that outputs one or more clock signals in which phase is controlled at a prescribed resolution with respect to received reference clock signals, comprising: a first delay locked loop that is feedback-controlled and that contains a first voltage-controlled delay line comprising delay buffers having a first type of propagation delay time concatenated in h stages and that receives a selected one of said reference clock signals; a second delay locked loop that is feedback-controlled and that contains i second voltage-controlled delay lines that are each connected to one of a respective output of i stages of outputs of said first voltage-controlled delay line and said selected at least one of said reference clock signals, each said second voltage-controlled delay line comprising delay buffers having a second type of propagation delay time concatenated in j stages; a third delay locked loop that is feedback-controlled and that contains a third voltage-controlled delay line that is composed of delay buffers having said second type of propagation delay time concatenated in k stages; and a selector that switches a clock signal from one of selected ones of stages of said first voltage-controlled delay line and said second voltage-controlled delay line to be an input into said third voltage-controlled delay line wherein, a delay control voltage or current for maintaining resolution that is generated by said third delay locked loop that feedback-controls said third voltage-controlled delay line is supplied to each of the delay buffers of each of said second voltage-controlled delay lines.
Claim 3
Dependent Claim
77 words
A digital phase control circuit according to claim 1 , wherein at least one voltage-controlled delay line of said second voltage-controlled delay lines is feedback-controlled by said second delay locked loop, and a delay control voltage or current for maintaining resolution that is generated by said second delay locked loop that feedback-controls said one voltage-controlled delay line is supplied to each delay buffer of the other second voltage-controlled delay lines to control the phase of clock signals.
Claim 4
Dependent Claim
30 words
A digital phase control circuit according to claim 1 , wherein said resolution is set to 1/n (where n is an integer) of the period of said reference clock signals.
Claim 5
Dependent Claim
230 words
A digital phase control circuit that outputs one or more clock signals in which phase is controlled at a prescribed resolution with respect to received reference clock signals, comprising: a first delay locked loop that is feedback-controlled and that contains a first voltage-controlled delay line comprising delay buffers having a first type of propagation delay time concatenated in a plurality of stages and that receives at least one of said reference clock signals and a current control circuit for adjusting current of a delay control signal; a second delay locked loop that is feedback-controlled and that contains a second voltage-controlled delay line comprising delay buffers having a second type of propagation delay time concatenated in a plurality of stages and a current control circuit for adjusting current of a delay control signal; a cyclic delay circuit that is connected to the input side of said second voltage-controlled delay line comprising variable delay buffers concatenated in a plurality of stages, a switch circuit for switching between said first type of propagation delay time and said second type of propagation delay time, and a current control circuit for adjusting current of a delay control signal; and a selector that receives as inputs a clock signal from each stage of said first voltage-controlled delay line and outputs a selected one of said clock signals to be an input into said cyclic delay circuit.
Claim 6
Dependent Claim
230 words
A digital phase control circuit that outputs one or more clock signals in which phase is controlled at a prescribed resolution with respect to received reference clock signals, comprising: a first delay locked loop that is feedback-controlled and that contains a first voltage-controlled delay line comprising delay buffers having a first type of propagation delay time concatenated in a plurality of stages and that receives at least one of said reference clock signals and a current control circuit for adjusting current of a delay control signal; a second delay locked loop that is feedback-controlled and that contains a second voltage-controlled delay line comprising delay buffers having a second type of propagation delay time concatenated in a plurality of stages and a current control circuit for adjusting current of a delay control signal; a cyclic delay circuit that is connected to the input side of said second voltage-controlled delay line comprising variable delay buffers concatenated in a plurality of stages, a switch circuit for switching between said first type of propagation delay time and said second type of propagation delay time, and a current control circuit for adjusting current of a delay control signal; and a selector that receives as inputs a clock signal from each stage of said first voltage-controlled delay line and outputs a selected one of said clock signals to be an input into said cyclic delay circuit.
Claim 7
Dependent Claim
30 words
A digital phase control circuit according to claim 4 , wherein said resolution is set to 1/n (where n is an integer) of the period of said reference clock signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-12-09 | 2006-06-10 | 2006-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-12-09 | 2010-06-10 | 2010-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-12-09 | 2014-06-10 | 2014-12-10 | $7700.00 | Window Closed / Lapsed |