US7095354B2 — Very linear wide-range pipelined charge-to-digita…

Claim 1

Independent Claim 89 words

A multi-channel analog to digital conversion circuit comprising: a plurality of linearized channels wherein each channel comprises a multi-stage pipelined charge-to-digital converter and an integrating capacitor within each stage of the multi-stage converter, wherein analog residue is processed by subsequent analog to digital converter stages; and wherein each stage of respective linearized channels is configured for calculating gain and offset of each respective stage and wherein the gain and offset of a given stage is calculated using a result of a calculated gain and/or offset from an adjacent stage.

Claim 2

Dependent Claim 89 words

A multi-channel analog to digital conversion circuit comprising: a plurality of linearized channels wherein each channel comprises a multi-stage pipelined charge-to-digital converter and an integrating capacitor within each stage of the multi-stage converter, wherein analog residue is processed by subsequent analog to digital converter stages; and wherein each stage of respective linearized channels is configured for calculating gain and offset of each respective stage and wherein the gain and offset of a given stage is calculated using a result of a calculated gain and/or offset from an adjacent stage.

Claim 3

Dependent Claim 90 words

The multichannel analog to digital conversion circuit of claim 1 , wherein each of the integrate and fold amplifier stages comprises: an amplifier having an input voltage and output voltage, an inverting terminal connected to the input voltage; the integrating capacitor connected between the inverting capacitor connected between the inverting terminal and an output terminal of the amplifier; a charge subtracting circuit selectively coupled to the inverting terminal and wherein the charge subtracting circuit is configured for removing a respective predetermined charge a number of times from the integrator capacitor.

Claim 4

Dependent Claim 42 words

The multi-channel analog to digital conversion circuit of claim 2 , wherein signals outside of a linear operating range of the amplifier are sensed using a comparator and when the signal outside the linear operating range is sensed, the stage is reset.

Claim 5

Dependent Claim 29 words

The multichannel analog to digital conversion circuit of claim 3 , wherein a threshold voltage is selected to indicate a boundary outside a linear operating range of the amplifier.

Claim 6

Dependent Claim 29 words

The multichannel analog to digital conversion circuit of claim 4 , further comprising a reset switch responsive to detection of an out of bounds output voltage of the amplifier.

Claim 7

Dependent Claim 26 words

The multichannel analog to digital conversion circuit of claim 5 , wherein the reset switch closes one when the out of bounds output voltage is detected.

Claim 8

Dependent Claim 28 words

The multichannel analog to digital conversion circuit of claim 5 , wherein the reset switch closes for a duration when the out of bounds output voltage is detected.

Claim 9

Dependent Claim 55 words

The multi-channel analog to digital conversion circuit of claim 1 , further comprising a disconnection means for disconnecting a given stage from a prior stage, injecting ratio metric analog signals into the given stage, using the given stage and subsequent stages to determine the calculated gain and offset of the given stage or subsequent stages.

Claim 10

Dependent Claim 72 words

The multi-channel analog to digital conversion circuit of claim 1 , further comprising a sensor coupled to a first stage of the multi-stage converter, wherein during signal transfer from the sensor to the first stage the sensor is disconnected from the converter to enable increase in stage bandwidth during signal transfer and wherein respective other stages are reconfigured to high stage bandwidth mode while transferring respective analog residue to the subsequent stage.

Claim 11

Dependent Claim 60 words

The multi-channel analog to digital conversion circuit of claim 9 , wherein the sensor is disconnected from the converter using a switch during a charge removal period and when the sensor is disconnected, a sensor signal is accumulated and stored on the sensor or the sensor signal is accumulated and stored on an external storage element such as a capacitor.

Claim 12

Dependent Claim 31 words

The multi-channel analog to digital conversion circuit of claim 10 , wherein the sensor is disconnected from the converter when the first stage writes its analog output to a second stage.

Claim 13

Dependent Claim 31 words

The multi-channel analog to digital conversion circuit of claim 1 , further comprising an over-range prevention circuit used to control the integration of a signal by using a discharge current limiter.

Claim 14

Dependent Claim 24 words

The multi-channel analog to digital conversion circuit of claim 12 , wherein the over-range prevention circuit is configured for charge removal independent of signal.

Claim 15

Dependent Claim 35 words

The multi-channel analog to digital conversion circuit of claim 12 , wherein the over range current circuit is disabled to allow the stage to fully process input signal and disconnect input while transferring analog residue.

Claim 16

Dependent Claim 58 words

The multi-channel analog to digital conversion circuit of claim 1 , further comprising a sensor coupled to a first stage of the multi-stage converter and a monitoring means for monitoring changes in linearization offset and gain in converter by replicating offset and gain drift sources on the monitoring means wherein the monitoring means is uncoupled to the sensor.

Claim 17

Dependent Claim 52 words

The multichannel analog to digital conversion circuit of claim 15 wherein the monitoring means further comprises at least one tracker channel coupled to the plurality of linearized channels to monitor changes in gain of the linearized channels by swapping a fold source of a sensor channel with that of the tracker channel.

Claim 18

Dependent Claim 20 words

The multichannel analog to digital conversion circuit of claim 16 , wherein the current discharge control circuit comprises fold sharing.

Claim 19

Dependent Claim 23 words

The multichannel analog to digital conversion circuit of claim 17 , wherein the fold current sharing comprises on demand, pre-arranged or grid timesharing.

Claim 20

Dependent Claim 29 words

The multi-channel analog to digital conversion circuit of claim 1 , further comprising means for measurement and calibration of a fold source using a known, well characterized input signal.

Claim 21

Dependent Claim 56 words

The multi-channel analog to digital conversion circuit of claim 1 , further comprising a plurality of monitoring circuits coupled to a plurality of multi-stage analog to digital conversion circuits forming a multiple converter configuration, wherein the plurality of monitoring circuits a monitoring means for monitoring changes in linearization offset and gain in the multiple converter configuration.

Claim 22

Dependent Claim 38 words

The multi-channel analog to digital conversion circuit of claim 1 wherein each multi-stage pipelined charge-to-digital converter comprises a first stage current-processing integrate and fold amplifier stage coupled in series with three subsequent voltage-processing integrate and fold amplifier stages.

Claim 23

Dependent Claim 54 words

The multichannel analog to digital conversion circuit of claim 21 , further comprising a tracker channel coupled to then plurality of channels to monitor gain and offset drift of the respective channels and wherein the gain and offset drift are due to temperature, drift across multiple integrated circuits, current leakage or a combination thereof.

Claim 24

Independent Claim 182 words

A method for analog to digital conversion using a multichannel analog to digital conversion circuit and wherein the multichannel analog to digital conversion circuit includes a plurality of linearized channels wherein each channel comprises a multi-stage pipelined charge-to-digital converter and an integrating capacitor within each stage of the four-stage converter, the integrating capacitor storing a charge proportional to an integral of an input charge, the method comprising: disconnecting input to a first stage of the multi-stage converter during subsequent stage sampling of an output from the first stage; presampling the output from the first stage in subsequent stages; disabling of charge removal in the first stage during subsequent stage sampling to avoid sample corruption; limiting discharge-current within respective stages using a discharge-current limiter; bypassing of the discharge-current limiter at timed intervals to insure all sampled charge is counted by end of each respective integration period; disabling of charge removal in a present-stage when bypassing in that stage; opening of present-stage bypass and/or discharge switches when sampling by subsequent stages; and, disabling of present-stage charge removal prior to and during subsequent stage sampling.

Claim 25

Independent Claim 182 words

A method for analog to digital conversion using a multichannel analog to digital conversion circuit and wherein the multichannel analog to digital conversion circuit includes a plurality of linearized channels wherein each channel comprises a multi-stage pipelined charge-to-digital converter and an integrating capacitor within each stage of the four-stage converter, the integrating capacitor storing a charge proportional to an integral of an input charge, the method comprising: disconnecting input to a first stage of the multi-stage converter during subsequent stage sampling of an output from the first stage; presampling the output from the first stage in subsequent stages; disabling of charge removal in the first stage during subsequent stage sampling to avoid sample corruption; limiting discharge-current within respective stages using a discharge-current limiter; bypassing of the discharge-current limiter at timed intervals to insure all sampled charge is counted by end of each respective integration period; disabling of charge removal in a present-stage when bypassing in that stage; opening of present-stage bypass and/or discharge switches when sampling by subsequent stages; and, disabling of present-stage charge removal prior to and during subsequent stage sampling.

Claim 26

Dependent Claim 188 words

A multi-channel analog to digital conversion circuit comprising: a plurality of channels, wherein each channel comprises a multi-stage pipelined charge-to-digital converter and an integrating capacitor within each stage of the multi-stage converter, the integrating capacitor storing a charge proportional to an integral of an input charge and wherein each stage of the respective linearized channels is configured for calculating gain and offset for each stage in the channel to be used in subsequent integration periods; wherein each of the multi-stage pipelined charge-to-digital converter comprises at least one stage current-processing integrate and fold amplifier stage coupled in series with a plurality of subsequent voltage-processing integrate and fold amplifier stages; and, each of the integrate and fold amplifier stages comprises: an amplifier having an input voltage and output voltage, an inverting terminal connected to the input voltage; the integrating capacitor connected between the inverting capacitor connected between the inverting terminal and an output terminal of the amplifier; and, a charge subtracting circuit selectively coupled to the inverting terminal and wherein the charge subtracting circuit is configured for removing a respective predetermined charge a number of times from the integrator capacitor.

Claim 27

Dependent Claim 188 words

A multi-channel analog to digital conversion circuit comprising: a plurality of channels, wherein each channel comprises a multi-stage pipelined charge-to-digital converter and an integrating capacitor within each stage of the multi-stage converter, the integrating capacitor storing a charge proportional to an integral of an input charge and wherein each stage of the respective linearized channels is configured for calculating gain and offset for each stage in the channel to be used in subsequent integration periods; wherein each of the multi-stage pipelined charge-to-digital converter comprises at least one stage current-processing integrate and fold amplifier stage coupled in series with a plurality of subsequent voltage-processing integrate and fold amplifier stages; and, each of the integrate and fold amplifier stages comprises: an amplifier having an input voltage and output voltage, an inverting terminal connected to the input voltage; the integrating capacitor connected between the inverting capacitor connected between the inverting terminal and an output terminal of the amplifier; and, a charge subtracting circuit selectively coupled to the inverting terminal and wherein the charge subtracting circuit is configured for removing a respective predetermined charge a number of times from the integrator capacitor.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2009-08-21	2010-02-20	2010-08-22	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2013-08-21	2014-02-20	2014-08-22	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2017-08-21	2018-02-20	2018-08-22	$7700.00	Window Closed / Lapsed

Very linear wide-range pipelined charge-to-digital converter

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