Method and apparatus for numeric optimization of the control of a delay-locked loop in a network device

Claim 3

A method as recited in claim 1 , wherein the provided number of clock cycles comprises at least 32 clock cycles.

Claim 4

A method as recited in claim 2 , wherein the provided number of clock cycles comprises 64 clock cycles.

Claim 5

A method as recited in claim 1 , wherein the step of repeating the determining and calculating steps is performed a sufficient number of times to remove effects of low frequency power supply instability from the representative value.

Claim 6

A method as recited in claim 4 , wherein the determining, calculating and repeating steps are performed in the slave DLL modules after the step of forwarding the representative value.

Claim 7

A delay offset module for setting a delay offset in slave Delay-Locked Loop (DLL) modules by a master DLL module, said module comprising: determining means for determining whether a delay tap value needs to be adjusted based on a comparison with a reference clock signal; calculating means for calculating a delay offset value to correct the delay tap value; timing means for measuring a predetermined time period comprising a provided number of clock cycles of the reference clock signal; holding means for holding multiple calculated delay offset values determined by the calculating means over the predetermined time period; representative means for obtaining a representative value of the held calculated delay offset values, wherein the representative value is obtained by the representative means by averaging all of the held calculated delay offset values during the provided number of clock cycles; and forwarding means for forwarding the representative value.

Claim 8

A delay offset module for setting a delay offset in slave Delay-Locked Loop (DLL) modules by a master DLL module, said module comprising: determining means for determining whether a delay tap value needs to be adjusted based on a comparison with a reference clock signal; calculating means for calculating a delay offset value to correct the delay tap value; timing means for measuring a predetermined time period comprising a provided number of clock cycles of the reference clock signal; holding means for holding multiple calculated delay offset values determined by the calculating means over the predetermined time period; representative means for obtaining a representative value of the held calculated delay offset values, wherein the representative value is obtained by the representative means by averaging all of the held calculated delay offset values during the provided number of clock cycles; and forwarding means for forwarding the representative value.

Claim 9

A module as recited in claim 6 , wherein the provided number of clock cycles comprises at least 32 clock cycles.

Claim 10

A module as recited in claim 7 , wherein the provided number of clock cycles comprises 64 clock cycles.

Claim 11

A module as recited in claim 6 , wherein the predetermined time period comprises a sufficient length of time to remove effects of low frequency power supply instability from the representative value.

Claim 12

A module as recited in claim 6 , wherein the calculating, timing, holding and representative means are contained in each of the slave DLL modules.

Claim 13

A delay offset module for setting a delay offset in slave Delay-Locked Loop (DLL) modules by a master DLL module, said module comprising: an adjustment determiner for determining whether a delay tap value needs to be adjusted based on a comparison with a reference clock signal; a calculating means for calculating a delay offset value to correct the delay tap value; a timer for measuring a predetermined time period, the predetermined time period comprising a provided number of clock cycles of the reference clock signal; a holding memory for holding multiple calculated delay offset values determined by the calculating means over the predetermined time period; a representative value calculator for obtaining a representative value of the held calculated delay offset values, wherein the representative value is obtained by the representative value calculator by averaging all of the held calculated delay offset values during the provided number of clock cycles; and a forwarder for forwarding the representative value.

Claim 14

A delay offset module for setting a delay offset in slave Delay-Locked Loop (DLL) modules by a master DLL module, said module comprising: an adjustment determiner for determining whether a delay tap value needs to be adjusted based on a comparison with a reference clock signal; a calculating means for calculating a delay offset value to correct the delay tap value; a timer for measuring a predetermined time period, the predetermined time period comprising a provided number of clock cycles of the reference clock signal; a holding memory for holding multiple calculated delay offset values determined by the calculating means over the predetermined time period; a representative value calculator for obtaining a representative value of the held calculated delay offset values, wherein the representative value is obtained by the representative value calculator by averaging all of the held calculated delay offset values during the provided number of clock cycles; and a forwarder for forwarding the representative value.

Claim 15

A module as recited in claim 11 , wherein the provided number of clock cycles comprises at least 32 clock cycles.

Claim 16

A module as recited in claim 12 , wherein the provided number of clock cycles comprises 64 clock cycles.

Claim 17

A module as recited in claim 11 , wherein the predetermined time period comprises a sufficient length of time to remove effects of low frequency power supply instability from the representative value.

Claim 18

A module as recited in claim 11 , wherein the calculator, the timer, the holding memory, the representative value calculator are contained in each of the slave DLL modules.