Method and apparatus for digital phase generation at high frequencies

Claim 3

The method of generating multi-phase clocks of claim 1 , further comprising adjusting the alignment magnitude to a predetermined amount and adjusting the phase delay magnitude proportional to the phase difference until the phase difference is substantially near zero.

Claim 4

The method of generating multi-phase clocks of claim 2 , wherein the predetermined amount is substantially near zero.

Claim 5

The method of generating multi-phase clocks of claim 1 , further comprising adjusting the phase delay magnitude to a predetermined amount and adjusting the alignment magnitude proportional to the phase difference until the phase difference is substantially near zero.

Claim 6

The method of generating multi-phase clocks of claim 4 , wherein the predetermined amount is substantially near a minimum delay.

Claim 9

The method of generating multi-phase clocks of claim 6 , further comprising adjusting the alignment magnitude to a predetermined amount and adjusting the phase delay magnitude proportional to the phase difference until the phase difference is substantially near zero.

Claim 10

The method of generating multi-phase clocks of claim 7 , wherein the predetermined amount is substantially near zero.

Claim 11

The method of generating multi-phase clocks of claim 6 , further comprising adjusting the phase delay magnitude to a predetermined amount and adjusting the alignment magnitude proportional to the phase difference until the phase difference is substantially near zero.

Claim 12

The method of generating multi-phase clocks of claim 9 , wherein the predetermined amount is substantially near a minimum delay.

Claim 15

The method of generating multi-phase clocks of claim 11 , further comprising adjusting the alignment magnitude to a predetermined amount and adjusting the cycle delay magnitude proportional to the phase difference until the phase difference is substantially near zero.

Claim 16

The method of generating multi-phase clocks of claim 12 , wherein the predetermined amount is substantially near zero.

Claim 17

The method of generating multi-phase clocks of claim 11 , further comprising adjusting the cycle delay magnitude to a predetermined amount and adjusting the alignment magnitude proportional to the phase difference until the phase difference is substantially near zero.

Claim 18

The method of generating multi-phase clocks of claim 14 , wherein the predetermined amount is substantially near a minimum delay.

Claim 19

The method of generating multi-phase clocks of claim 11 , wherein the tap alignment delay for each of the N delay taps substantially equals (1−the tap delay magnitude)*the alignment magnitude.

Claim 20

The method of generating multi-phase clocks of claim 11 , wherein N equals one and the tap delay magnitude for a first tap substantially equals ½.

Claim 21

The method of generating multi-phase clocks of claim 11 , wherein N equals three and the tap delay magnitude for a first tap substantially equals ¼, the tap delay magnitude for a second tap substantially equals ½, and the tap delay magnitude for a third tap substantially equals ¾.

Claim 22

The method of generating multi-phase clocks of claim 11 , wherein N equals two and the tap delay magnitude for a first tap substantially equals ⅓ and the tap delay magnitude for a second tap substantially equals ⅔.

Claim 23

The method of generating multi-phase clocks of claim 11 , wherein N equals two and the tap delay magnitude for a first tap substantially equals ¼ and the tap delay magnitude for a second tap substantially equals ¾.

Claim 24

A phase generator, comprising: a first delay line configured to generate a first phase signal with a phase delay magnitude relative to a clock input; a second delay line configured to generate a last phase signal with the phase delay magnitude relative to the first phase signal; a first phase aligner configured to generate a first aligned phase signal with an alignment magnitude relative to the clock input; a second phase aligner configured to generate a second aligned phase signal with substantially ½ the alignment magnitude relative to the first phase signal; and a phase detector configured to compare the first aligned phase signal and the last phase signal, generate a phase adjustment signal for modifying the phase delay magnitude, and generate an alignment adjustment signal for modifying the alignment magnitude.

Claim 25

A phase generator, comprising: a first delay line configured to generate a first phase signal with a phase delay magnitude relative to a clock input; a second delay line configured to generate a last phase signal with the phase delay magnitude relative to the first phase signal; a first phase aligner configured to generate a first aligned phase signal with an alignment magnitude relative to the clock input; a second phase aligner configured to generate a second aligned phase signal with substantially ½ the alignment magnitude relative to the first phase signal; and a phase detector configured to compare the first aligned phase signal and the last phase signal, generate a phase adjustment signal for modifying the phase delay magnitude, and generate an alignment adjustment signal for modifying the alignment magnitude.

Claim 26

The phase generator of claim 21 , wherein the phase detector is configured to adjust the alignment magnitude to a predetermined amount and adjust the phase delay magnitude so the first aligned phase signal and the last phase signal are substantially in phase.

Claim 27

The phase generator of claim 22 , wherein the predetermined amount is substantially near zero.

Claim 28

The phase generator of claim 21 , wherein the phase detector is configured to adjust the phase delay magnitude to a predetermined amount and adjust the alignment magnitude so the first aligned phase signal and the last phase signal are substantially in phase.

Claim 29

The phase generator of claim 24 , wherein the predetermined amount is substantially near a minimum delay.

Claim 30

The phase generator of claim 21 , wherein the first delay line and the second delay line each comprise a coarse delay line with a coarse delay magnitude and a fine delay line with a fine delay magnitude, wherein the sum of the coarse delay magnitude and the fine delay magnitude substantially equals the phase delay magnitude.

Claim 31

A phase generator, comprising: a first delay line configured to generate a first phase signal with a phase delay magnitude relative to a clock input; a second delay line configured to generate a second phase signal with the phase delay magnitude relative to the first phase signal; a third delay line configured to generate a third phase signal with the phase delay magnitude relative to the second phase signal; a fourth delay line configured to generate a last phase signal with the phase delay magnitude relative to the third phase signal; a first phase aligner configured to generate a first aligned phase signal with an alignment magnitude relative to the clock input; a second phase aligner configured to generate a second aligned phase signal with substantially ¾ the alignment magnitude relative to the first phase signal; a third phase aligner configured to generate a third aligned phase signal with substantially ½ the alignment magnitude relative to the second phase signal; a fourth phase aligner configured to generate a fourth aligned phase signal with substantially ¼ the alignment magnitude relative to the third phase signal; and a phase detector configured to compare the first aligned phase signal and the last phase signal, generate a phase adjustment signal for modifying the phase delay magnitude, and generate an alignment adjustment signal for modifying the alignment magnitude.

Claim 32

A phase generator, comprising: a first delay line configured to generate a first phase signal with a phase delay magnitude relative to a clock input; a second delay line configured to generate a second phase signal with the phase delay magnitude relative to the first phase signal; a third delay line configured to generate a third phase signal with the phase delay magnitude relative to the second phase signal; a fourth delay line configured to generate a last phase signal with the phase delay magnitude relative to the third phase signal; a first phase aligner configured to generate a first aligned phase signal with an alignment magnitude relative to the clock input; a second phase aligner configured to generate a second aligned phase signal with substantially ¾ the alignment magnitude relative to the first phase signal; a third phase aligner configured to generate a third aligned phase signal with substantially ½ the alignment magnitude relative to the second phase signal; a fourth phase aligner configured to generate a fourth aligned phase signal with substantially ¼ the alignment magnitude relative to the third phase signal; and a phase detector configured to compare the first aligned phase signal and the last phase signal, generate a phase adjustment signal for modifying the phase delay magnitude, and generate an alignment adjustment signal for modifying the alignment magnitude.

Claim 33

The phase generator of claim 27 , wherein the phase detector is configured to adjust the alignment magnitude to a predetermined amount and adjust the phase delay magnitude so the first aligned phase signal and the last phase signal are substantially in phase.

Claim 34

The phase generator of claim 28 , wherein the predetermined amount is substantially near zero.

Claim 35

The phase generator of claim 27 , wherein the phase detector is configured to adjust the phase delay magnitude to a predetermined amount and adjust the alignment magnitude so the first aligned phase signal and the last phase signal are substantially in phase.

Claim 36

The phase generator of claim 30 , wherein the predetermined amount is substantially near a minimum delay.

Claim 37

The phase generator of claim 27 , wherein the first delay line, the second delay line, the third delay line, and the fourth delay line each comprise a coarse delay line with a coarse delay magnitude and a fine delay line with a fine delay magnitude, wherein the sum of the coarse delay magnitude and the fine delay magnitude substantially equals the phase delay magnitude.

Claim 38

A phase generator, comprising: an adjustable delay line configured for generating a last phase signal by delaying a clock input by a cycle delay magnitude, the adjustable delay line including N delay taps, each of the N delay taps having a tap delay magnitude equal to a fractional amount of the cycle delay magnitude; a first phase aligner configured for generating a first aligned phase signal by delaying the clock input by an alignment magnitude; N phase aligners, each of the N phase aligners operably coupled to a corresponding delay tap of the N delay taps and configured to generate a phase aligned signal with a tap alignment delay relative to its delay tap; and a phase detector configured to compare the first aligned phase signal and the last phase signal, generate a phase adjustment signal for modifying the cycle delay magnitude, and generate an alignment adjustment signal for modifying the alignment magnitude.

Claim 39

A phase generator, comprising: an adjustable delay line configured for generating a last phase signal by delaying a clock input by a cycle delay magnitude, the adjustable delay line including N delay taps, each of the N delay taps having a tap delay magnitude equal to a fractional amount of the cycle delay magnitude; a first phase aligner configured for generating a first aligned phase signal by delaying the clock input by an alignment magnitude; N phase aligners, each of the N phase aligners operably coupled to a corresponding delay tap of the N delay taps and configured to generate a phase aligned signal with a tap alignment delay relative to its delay tap; and a phase detector configured to compare the first aligned phase signal and the last phase signal, generate a phase adjustment signal for modifying the cycle delay magnitude, and generate an alignment adjustment signal for modifying the alignment magnitude.

Claim 40

The phase generator of claim 33 , wherein the phase detector is configured to adjust the alignment magnitude to a predetermined amount and adjust the cycle delay magnitude so the first aligned phase signal and the last phase signal are substantially in phase.

Claim 41

The phase generator of claim 34 , wherein the predetermined amount is substantially near zero.

Claim 42

The phase generator of claim 33 , wherein the phase detector is configured to adjust the cycle delay magnitude to a predetermined amount and adjust the alignment magnitude so the first aligned phase signal and the last phase signal are substantially in phase.

Claim 43

The phase generator of claim 36 , wherein the predetermined amount is substantially near a minimum delay.

Claim 44

The phase generator of claim 33 , wherein the adjustable delay line comprises a coarse delay line with a coarse delay magnitude and a fine delay line with a fine delay magnitude, wherein the sum of the coarse delay magnitude and the fine delay magnitude substantially equals the cycle delay magnitude.

Claim 45

The phase generator of claim 33 , wherein the tap alignment delay for each of the N delay taps substantially equals (1−the tap delay magnitude)*the alignment magnitude.

Claim 46

The phase generator of claim 33 , wherein N equals one and the tap delay magnitude a first tap substantially equals ½.

Claim 47

The phase generator of claim 33 , wherein N equals three and the tap delay magnitude for a first tap substantially equals ¼, the tap delay magnitude fore a second tap substantially equals ½, and the tap delay magnitude for a third tap substantially equals ¾.

Claim 48

The phase generator of claim 33 , wherein N equals two and the tap delay magnitude for a first tap substantially equals ⅓ and the tap delay magnitude for a second tap substantially equals ⅔.

Claim 49

The phase generator of claim 33 , wherein N equals two and the tap delay magnitude for a first tap substantially equals ¼ and the tap delay magnitude for ae second tap substantially equals ¾.

Claim 50

The phase generator of claim 33 , wherein the adjustable delay line comprises a coarse delay line with a coarse delay magnitude and a fine delay line with a fine delay magnitude, wherein the sum of the coarse delay magnitude and the fine delay magnitude substantially equals the cycle delay magnitude.

Claim 51

A semiconductor device including at least one phase generator, the at least one phase generator comprising: an adjustable delay line configured for generating a full cycle delay signal by delaying a clock input by a cycle delay magnitude, the adjustable delay line including N delay taps, each of the N delay taps having a tap delay magnitude equal to a fractional amount of the cycle delay magnitude; a first phase aligner configured for generating a first aligned phase signal by delaying the clock input by an alignment magnitude; N phase aligners, each of the N phase aligners operably coupled to a corresponding delay tap of the N delay taps and configured to generate a phase aligned signal with a tap alignment delay relative to its delay tap; and a phase detector configured to compare the first aligned phase signal and the full cycle delay signal, generate a phase adjustment signal for modifying the cycle delay magnitude, and generate an alignment adjustment signal for modifying the alignment magnitude.

Claim 52

A semiconductor device including at least one phase generator, the at least one phase generator comprising: an adjustable delay line configured for generating a full cycle delay signal by delaying a clock input by a cycle delay magnitude, the adjustable delay line including N delay taps, each of the N delay taps having a tap delay magnitude equal to a fractional amount of the cycle delay magnitude; a first phase aligner configured for generating a first aligned phase signal by delaying the clock input by an alignment magnitude; N phase aligners, each of the N phase aligners operably coupled to a corresponding delay tap of the N delay taps and configured to generate a phase aligned signal with a tap alignment delay relative to its delay tap; and a phase detector configured to compare the first aligned phase signal and the full cycle delay signal, generate a phase adjustment signal for modifying the cycle delay magnitude, and generate an alignment adjustment signal for modifying the alignment magnitude.

Claim 53

The phase generator of claim 45 , wherein the phase detector is configured to adjust the alignment magnitude to a predetermined amount and adjust the cycle delay magnitude so the first aligned phase signal and the full cycle delay signal are substantially in phase.

Claim 54

The phase generator of claim 46 , wherein the predetermined amount is substantially near zero.

Claim 55

The phase generator of claim 45 , wherein the phase detector is configured to adjust the cycle delay magnitude to a predetermined amount and adjust the alignment magnitude so the first aligned phase signal and the full cycle delay signal are substantially in phase.

Claim 56

The phase generator of claim 48 , wherein the predetermined amount is substantially near a minimum delay.

Claim 57

A semiconductor wafer, comprising: at least one semiconductor device including at least one phase generator, the at least one phase generator comprising: an adjustable delay line configured for generating a full cycle delay signal by delaying a clock input by a cycle delay magnitude, the adjustable delay line including N delay taps, each of the N delay taps having a tap delay magnitude equal to a fractional amount of the cycle delay magnitude; a first phase aligner configured for generating a first aligned phase signal by delaying the clock input by an alignment magnitude; N phase aligners, each of the N phase aligners operably coupled to a corresponding delay tap of the N delay taps and configured to generate a phase aligned signal with a tap alignment delay relative to its delay tap; and a phase detector configured to compare the first aligned phase signal and the full cycle delay signal, generate a phase adjustment signal for modifying the cycle delay magnitude, and generate an alignment adjustment signal for modifying the alignment magnitude.

Claim 58

A semiconductor wafer, comprising: at least one semiconductor device including at least one phase generator, the at least one phase generator comprising: an adjustable delay line configured for generating a full cycle delay signal by delaying a clock input by a cycle delay magnitude, the adjustable delay line including N delay taps, each of the N delay taps having a tap delay magnitude equal to a fractional amount of the cycle delay magnitude; a first phase aligner configured for generating a first aligned phase signal by delaying the clock input by an alignment magnitude; N phase aligners, each of the N phase aligners operably coupled to a corresponding delay tap of the N delay taps and configured to generate a phase aligned signal with a tap alignment delay relative to its delay tap; and a phase detector configured to compare the first aligned phase signal and the full cycle delay signal, generate a phase adjustment signal for modifying the cycle delay magnitude, and generate an alignment adjustment signal for modifying the alignment magnitude.

Claim 59

The phase generator of claim 50 , wherein the phase detector is configured to adjust the alignment magnitude to a predetermined amount and adjust the cycle delay magnitude so the first aligned phase signal and the full cycle delay signal are substantially in phase.

Claim 60

The phase generator of claim 51 , wherein the predetermined amount is substantially near zero.

Claim 61

The phase generator of claim 51 , wherein the phase detector is configured to adjust the cycle delay magnitude to a predetermined amount and adjust the alignment magnitude so the first aligned phase signal and the full cycle delay signal are substantially in phase.

Claim 62

The phase generator of claim 53 , wherein the predetermined amount is substantially near a minimum delay.

Claim 63

An electronic system, comprising: at least one input device; at least one output device; at least one processor; and at least one memory device comprising, at least one semiconductor memory including at least one phase generator, the at least one phase generator, comprising: an adjustable delay line configured for generating a full cycle delay signal by delaying a clock input by a cycle delay magnitude, the delay line including N delay taps, each of the N delay taps having a tap delay magnitude equal to a fractional amount of the cycle delay magnitude; a first phase aligner configured for generating a first aligned phase signal by delaying the clock input by an alignment magnitude; N phase aligners, each of the N phase aligners operably coupled to a corresponding delay tap of the N delay taps and configured to generate a phase aligned signal with a tap alignment delay relative to its delay tap; and a phase detector configured to compare the first aligned phase signal and the full cycle delay signal, generate a phase adjustment signal for modifying the cycle delay magnitude, and generate an alignment adjustment signal for modifying the alignment magnitude.

Claim 64

An electronic system, comprising: at least one input device; at least one output device; at least one processor; and at least one memory device comprising, at least one semiconductor memory including at least one phase generator, the at least one phase generator, comprising: an adjustable delay line configured for generating a full cycle delay signal by delaying a clock input by a cycle delay magnitude, the delay line including N delay taps, each of the N delay taps having a tap delay magnitude equal to a fractional amount of the cycle delay magnitude; a first phase aligner configured for generating a first aligned phase signal by delaying the clock input by an alignment magnitude; N phase aligners, each of the N phase aligners operably coupled to a corresponding delay tap of the N delay taps and configured to generate a phase aligned signal with a tap alignment delay relative to its delay tap; and a phase detector configured to compare the first aligned phase signal and the full cycle delay signal, generate a phase adjustment signal for modifying the cycle delay magnitude, and generate an alignment adjustment signal for modifying the alignment magnitude.

Claim 65

The phase generator of claim 55 , wherein the phase detector is configured to adjust the alignment magnitude to a predetermined amount and adjust the cycle delay magnitude so the first aligned phase signal and the full cycle delay signal are substantially in phase.

Claim 66

The phase generator of claim 56 , wherein the predetermined amount is substantially near zero.

Claim 67

The phase generator of claim 55 , wherein the phase detector is configured to adjust the cycle delay magnitude to a predetermined amount and adjust the alignment magnitude so the first aligned phase signal and the full cycle delay signal are substantially in phase.

Claim 68

The phase generator of claim 58 , wherein the predetermined amount is substantially near a minimum delay.