Abstract Provided is directed to a delay locked loop control circuit capable of reducing a test time and preventing a yield from being reduced, by preventing a failure due to a charge sharing and a failure in a specific frequency and voltage due to a noise of a feedback clock, by means of including: a level setting unit for setting an initial level of a locked state signal, which is decided whether or not phases of a reference clock and a feedback clock are aligned; a signal generation unit for generating a third control signal according to a first control signal comparing phases of the reference clock and the feedback clock, and a second control signal checking out phases of the reference clock and the feedback clock in every predetermined time; a level maintaining unit for maintaining a level of the locked state signal according to the locked state signal and a fourth control signal comparing a signal delaying the feedback clock for a predetermined time with the reference clock; a detection unit for varying a level of the locked state signal by detecting whether or not phases of a reference clock and a feedback clock are aligned according to the first to third control signals; and a control unit for controlling a variation of the locked state signal by means of the detection unit according to the fourth control signal.
A delay locked loop control circuit, comprising: a latch connected to a first node for latching a locked state signal; a level setting unit for setting an initial level of the locked state signal, which is decided whether or not phases of a reference clock and a feedback clock are aligned; a signal generation unit for generating a third control signal according to a first control signal, the first control signal is a phase difference indicating the result of phases comparison of the reference clock and the feedback clock, and a second control signal, the second control signal is for checking out phases of the reference clock and the feedback clock in every predetermined time; a level maintaining unit for maintaining a level of the locked state signal according to the locked state signal and a fourth control signal outputted from a phase detector, the fourth control signal is a phase difference indicating the result of phases comparison of a signal delaying the feedback clock for a predetermined time with the reference clock; a detection unit for varying a level of the locked state signal by detecting whether or not phases of the reference clock and the feedback clock are aligned according to the first to third control signals; and a control unit for controlling a variation of the locked state signal by means of the detection unit according to the fourth control signal.
Claim 2
Dependent Claim
234 words
A delay locked loop control circuit, comprising: a latch connected to a first node for latching a locked state signal; a level setting unit for setting an initial level of the locked state signal, which is decided whether or not phases of a reference clock and a feedback clock are aligned; a signal generation unit for generating a third control signal according to a first control signal, the first control signal is a phase difference indicating the result of phases comparison of the reference clock and the feedback clock, and a second control signal, the second control signal is for checking out phases of the reference clock and the feedback clock in every predetermined time; a level maintaining unit for maintaining a level of the locked state signal according to the locked state signal and a fourth control signal outputted from a phase detector, the fourth control signal is a phase difference indicating the result of phases comparison of a signal delaying the feedback clock for a predetermined time with the reference clock; a detection unit for varying a level of the locked state signal by detecting whether or not phases of the reference clock and the feedback clock are aligned according to the first to third control signals; and a control unit for controlling a variation of the locked state signal by means of the detection unit according to the fourth control signal.
Claim 3
Dependent Claim
51 words
The delay locked loop control circuit of claim 1 , wherein the level setting unit includes: an inverter for inverting a reset signal; and a PMOS transistor for setting the initial level of the locked state signal by applying a power supply voltage according to an output signal of the inverter.
Claim 4
Dependent Claim
66 words
The delay locked loop control circuit of claim 1 , wherein the level maintaining unit includes: a first PMOS transistor connected to a power supply terminal for applying the power supply voltage according to the locked state signal; and a second PMOS transistor connected between the first PMOS transistor and the first node, and operated according to the fourth control signal outputted from the phase detector.
Claim 5
Dependent Claim
34 words
The delay locked loop control circuit of claim 1 , wherein the detection unit includes a plurality of NMOS transistors driven according to the first to third control signals, respectively, and connected in series.
Claim 6
Dependent Claim
25 words
The delay locked loop control circuit of claim 1 , wherein the control unit includes a NMOS transistor driven according to the fourth control signal.