Input circuit provided in a semiconductor integrated circuit, used in high-speed small-amplitude signal transmission system

Claim 2

An input circuit provided in a semiconductor integrated circuit, comprising: a first transistor of a first conductivity type connected between an input node receiving a transmission signal and a first node and having a control electrode connected to a reference potential, a second transistor of a second conductivity type connected between a power supply voltage and said first node, said power supply voltage being different from said reference potential, an inverter having an input connected to said first node and an output connected to an output terminal, and means including at least one circuit component other than a conducting line and having an output coupled to a control electrode of said second transistor and responding to at least a potential on said first node for rendering said second transistor non-conductive when said first transistor is conductive, wherein said first transistor comprises a first nMOS transistor having a source connected to said input node, a drain connected to said first node and a gate connected to said reference potential, and said second transistor comprises a first pMOS transistor having a source connected to said power supply voltage, a drain connected to said first node, and a gate connected to said output of said means, and wherein said means includes a first switch connected between ground and a second node connected to a gate of said first pMOS transistor and controlled by said transmission signal to connect and disconnect between said ground and said second node, and a second switch connected between said power supply voltage and said second node and controlled by said potential on said first node to connect and disconnect between said power supply voltage and said second node, so that when said first switch is in a closed condition, said second switch is in an open condition, and when said second switch is in a closed condition, said first switch is in an open condition.

Claim 3

An input circuit claimed in claim 1 wherein said first switch comprises a second nMOS transistor having a source connected to ground, a drain connected to said gate of said first pMOS transistor, and a gate connected to receive said transmission signal, and said second switch comprises at least one second pMOS transistor having a source connected to said power supply voltage, a drain connected to said gate of said first pMOS transistor, and a gate connected to said first node.

Claim 4

An input circuit provided in a semiconductor integrated circuit, comprising: a first transistor of a first conductivity type connected between an input node receiving a transmission signal and a first node and having a control electrode connected to a reference potential, a second transistor of a second conductivity type connected between a power supply voltage and said first node, said power supply voltage being different from said reference potential, an inverter having an input connected to said first node and an output connected to an output terminal, and means including at least one circuit component other than a conducting line and having an output coupled to a control electrode of said second transistor and responding to at least a potential on said first node for rendering said second transistor non-conductive when said first transistor is conductive, wherein said first transistor comprises a first nMOS transistor having a source connected to said input node, a drain connected to said first node and a gate connected to said reference potential, and said second transistor comprises a first pMOS transistor having a source connected to said power supply voltage, a drain connected to said first node, and a gate connected to said output of said means, and wherein said means includes a first switch connected between ground and a second node connected to said gate of said first pMOS transistor and controlled by said transmission signal to connect and disconnect between said ground and said second node, and a second inverter having an input connected to said first node and an output connected to said gate of said first pMOS transistor, so that when said first switch is in a closed condition, said output of said second inverter is brought to a low level, and when said output of said second inverter is at a high level, said first switch is brought into an open condition.

Claim 5

An input circuit provided in a semiconductor integrated circuit, comprising: a first transistor of a first conductivity type connected between an input node receiving a transmission signal and a first node and having a control electrode connected to a reference potential, a second transistor of a second conductivity type connected between a power supply voltage and said first node, said power supply voltage being different from said reference potential, an inverter having an input connected to said first node and an output connected to an output terminal, and means including at least one circuit component other than a conducting line and having an output coupled to a control electrode of said second transistor and responding to at least a potential on said first node for rendering said second transistor non-conductive when said first transistor is conductive, wherein said first transistor comprises a first nMOS transistor having a source connected to said input node, a drain connected to said first node and a gate connected to said reference potential, and said second transistor comprises a first pMOS transistor having a source connected to said power supply voltage, a drain connected to said first node, and a gate connected to said output of said means, and wherein said means includes a first switch connected between ground and a second node connected to said gate of said first pMOS transistor and controlled by said transmission signal to connect and disconnect between said ground and said second node, and a second inverter having an input connected to said first node and an output connected to said gate of said first pMOS transistor, so that when said first switch is in a closed condition, said output of said second inverter is brought to a low level, and when said output of said second inverter is at a high level, said first switch is brought into an open condition.

Claim 6

An input circuit claimed in claim 3 wherein said first switch comprises a second nMOS transistor having a source connected to said ground, a drain connected to said gate of said first pMOS transistor, and a gate connected to receive said transmission signal, and wherein said second inverter comprises at least one second pMOS transistor having a source connected to said power supply voltage, a drain connected to said gate of said first pMOS transistor, and a gate connected to said first node, and a third pMOS transistor having a source connected to said ground, a drain connected to said gate of said first pMOS transistor, and a gate connected to said first node.

Claim 7

An input circuit provided in a semiconductor integrated circuit, comprising: a first transistor of a first conductivity type connected between an input node receiving a transmission signal and a first node and having a control electrode connected to a reference potential, a second transistor of a second conductivity type connected between a power supply voltage and said first node, said power supply voltage being different from said reference potential, an inverter having an input connected to said first node and an output connected to an output terminal, and means including at least one circuit component other than a conducting line and having an output coupled to a control electrode of said second transistor and responding to at least a potential on said first node for rendering said second transistor non-conductive when said first transistor is conductive, wherein said means includes a first switch connected between ground and a second node connected to said control electrode of said second transistor and controlled by said transmission signal to connect and disconnect between said ground and said second node, and a second switch connected between said power supply voltage and said second node and controlled by said potential on said first node to connect and disconnect between said power supply voltage and said second node, so that when said first switch is in a closed condition, said second switch is in an open condition, and when said second switch is in a closed condition, said first switch is in an open condition.

Claim 8

An input circuit provided in a semiconductor integrated circuit, comprising: a first transistor of a first conductivity type connected between an input node receiving a transmission signal and a first node and having a control electrode connected to a reference potential, a second transistor of a second conductivity type connected between a power supply voltage and said first node, said power supply voltage being different from said reference potential, an inverter having an input connected to said first node and an output connected to an output terminal, and means including at least one circuit component other than a conducting line and having an output coupled to a control electrode of said second transistor and responding to at least a potential on said first node for rendering said second transistor non-conductive when said first transistor is conductive, wherein said means includes a first switch connected between ground and a second node connected to said control electrode of said second transistor and controlled by said transmission signal to connect and disconnect between said ground and said second node, and a second switch connected between said power supply voltage and said second node and controlled by said potential on said first node to connect and disconnect between said power supply voltage and said second node, so that when said first switch is in a closed condition, said second switch is in an open condition, and when said second switch is in a closed condition, said first switch is in an open condition.

Claim 9

An input circuit provided in a semiconductor integrated circuit, comprising: a first transistor of a first conductivity type connected between an input node receiving a transmission signal and a first node and having a control electrode connected to a reference potential, a second transistor of a second conductivity type connected between a power supply voltage and said first node, said power supply voltage being different from said reference potential, an inverter having an input connected to said first node and an output connected to an output terminal, and means including at least one circuit component other than a conducting line and having an output coupled to a control electrode of said second transistor and responding to at least a potential on said first node for rendering said second transistor non-conductive when said first transistor is conductive, wherein said means includes a first switch connected between ground and a second node connected to said control electrode of said second transistor and controlled by said transmission signal to connect and disconnect between the ground and said second node, and a second inverter having an input connected to said first node and an output connected to said control electrode of said second transistor, so that when said first switch is in a closed condition, said output of said second inverter is brought to a low level, and when said output of said second inverter is at a high level, said first switch is brought into an open condition.

Claim 10

An input circuit provided in a semiconductor integrated circuit, comprising: a first transistor of a first conductivity type connected between an input node receiving a transmission signal and a first node and having a control electrode connected to a reference potential, a second transistor of a second conductivity type connected between a power supply voltage and said first node, said power supply voltage being different from said reference potential, an inverter having an input connected to said first node and an output connected to an output terminal, and means including at least one circuit component other than a conducting line and having an output coupled to a control electrode of said second transistor and responding to at least a potential on said first node for rendering said second transistor non-conductive when said first transistor is conductive, wherein said means includes a first switch connected between ground and a second node connected to said control electrode of said second transistor and controlled by said transmission signal to connect and disconnect between the ground and said second node, and a second inverter having an input connected to said first node and an output connected to said control electrode of said second transistor, so that when said first switch is in a closed condition, said output of said second inverter is brought to a low level, and when said output of said second inverter is at a high level, said first switch is brought into an open condition.

Claim 11

An input circuit provided in a semiconductor integrated circuit, comprising: a first transistor of a first conductivity type connected between an input node receiving a transmission signal and a first node and having a control electrode connected to a reference potential, a second transistor of a second conductivity type connected between a power supply voltage terminal and said first node, said power supply voltage being different from said reference potential, an inverter having an input connected to said first node and an output connected to an output terminal, and means including at least one circuit component other than a conducting line and having an output connected to a control electrode of said second transistor and responding to at least a potential on said first node for causing said potential of said first node to be equal to that of said transmission signal when said transmission signal is at a first level, wherein said first transistor comprises a first nMOS transistor having a source connected to said input node, a drain connected to said first node and a gate connected to said reference potential, and said second transistor comprises a first pMOS transistor having a source connected to said power supply voltage, a drain connected to said first node, and a gate connected to said output of said means, and wherein said means includes a first switch connected between ground and a second node connected to a gate of said first pMOS transistor and controlled by said transmission signal to connect and disconnect between said ground and said second node, and a second switch connected between said power supply voltage and said second node and controlled by said potential on said first node to connect and disconnect between said power supply voltage and said second node, so that when said first switch is in a closed condition, said second switch is in an open condition, and when said second switch is in a closed condition, said first switch is in an open condition.

Claim 12

An input circuit provided in a semiconductor integrated circuit, comprising: a first transistor of a first conductivity type connected between an input node receiving a transmission signal and a first node and having a control electrode connected to a reference potential, a second transistor of a second conductivity type connected between a power supply voltage terminal and said first node, said power supply voltage being different from said reference potential, an inverter having an input connected to said first node and an output connected to an output terminal, and means including at least one circuit component other than a conducting line and having an output connected to a control electrode of said second transistor and responding to at least a potential on said first node for causing said potential of said first node to be equal to that of said transmission signal when said transmission signal is at a first level, wherein said first transistor comprises a first nMOS transistor having a source connected to said input node, a drain connected to said first node and a gate connected to said reference potential, and said second transistor comprises a first pMOS transistor having a source connected to said power supply voltage, a drain connected to said first node, and a gate connected to said output of said means, and wherein said means includes a first switch connected between ground and a second node connected to a gate of said first pMOS transistor and controlled by said transmission signal to connect and disconnect between said ground and said second node, and a second switch connected between said power supply voltage and said second node and controlled by said potential on said first node to connect and disconnect between said power supply voltage and said second node, so that when said first switch is in a closed condition, said second switch is in an open condition, and when said second switch is in a closed condition, said first switch is in an open condition.

Claim 13

An input circuit claimed in claim 7 wherein said first switch comprises a second nMOS transistor having a source connected to ground, a drain connected to said gate of said first pMOS transistor, and a gate connected to receive said transmission signal, and said second switch comprises at least one second pMOS transistor having a source connected to said power supply voltage, a drain connected to said gate of said first pMOS transistor, and a gate connected to said first node.

Claim 14

An input circuit provided in a semiconductor integrated circuit, comprising: a first transistor of a first conductivity type connected between an input node receiving a transmission signal and a first node and having a control electrode connected to a reference potential, a second transistor of a second conductivity type connected between a power supply voltage terminal and said first node, said power supply voltage being different from said reference potential, an inverter having an input connected to said first node and an output connected to an output terminal, and means including at least one circuit component other than a conducting line and having an output connected to a control electrode of said second transistor and responding to at least a potential on said first node for causing potential of said first node to be equal to that of said transmission signal when said transmission signal is at a first level, wherein said first transistor comprises a first nMOS transistor having a source connected to said input node, a drain connected to said first node and a gate connected to said reference potential, and said second transistor comprises a first pMOS transistor having a source connected to said power supply voltage, a drain connected to said first node, and a gate connected to said output of said means, and wherein said means includes a first switch connected between ground and a second node connected to said gate of said first pMOS transistor and controlled by said transmission signal to connect and disconnect between said ground and said second node, and a second inverter having an input connected to said first node and an output connected to said gate of said first pMOS transistor, so that when said first switch is in a closed condition, said output of said second inverter is brought to a low level, and when said output of said second inverter is at a high level, said first switch is brought into an open condition.

Claim 15

An input circuit provided in a semiconductor integrated circuit, comprising: a first transistor of a first conductivity type connected between an input node receiving a transmission signal and a first node and having a control electrode connected to a reference potential, a second transistor of a second conductivity type connected between a power supply voltage terminal and said first node, said power supply voltage being different from said reference potential, an inverter having an input connected to said first node and an output connected to an output terminal, and means including at least one circuit component other than a conducting line and having an output connected to a control electrode of said second transistor and responding to at least a potential on said first node for causing potential of said first node to be equal to that of said transmission signal when said transmission signal is at a first level, wherein said first transistor comprises a first nMOS transistor having a source connected to said input node, a drain connected to said first node and a gate connected to said reference potential, and said second transistor comprises a first pMOS transistor having a source connected to said power supply voltage, a drain connected to said first node, and a gate connected to said output of said means, and wherein said means includes a first switch connected between ground and a second node connected to said gate of said first pMOS transistor and controlled by said transmission signal to connect and disconnect between said ground and said second node, and a second inverter having an input connected to said first node and an output connected to said gate of said first pMOS transistor, so that when said first switch is in a closed condition, said output of said second inverter is brought to a low level, and when said output of said second inverter is at a high level, said first switch is brought into an open condition.

Claim 16

An input circuit claimed in claim 9 wherein said first switch comprises a second nMOS transistor having a source connected to said ground, a drain connected to said gate of said first pMOS transistor, and a gate connected to receive said transmission signal, and wherein said second inverter comprises at least one second pMOS transistor having a source connected to said power supply voltage, a drain connected to said gate of said first pMOS transistor, and a gate connected to said first node, and a third nMOS transistor having a source connected to said ground, a drain connected to said gate of said first pMOS transistor, and a gate connected to said first node.