Patent US7007125B2 successfully refreshed from Google Patents.
US7007125B2
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Pass through circuit for reduced memory latency in a multiprocessor system
Assignee: Lenovo International Ltd
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Filing: 2003-06-24
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Granted: 2006-02-28
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Expires: 2023-06-24
Abstract
Abstract A technique and mechanism for reducing memory latency asymmetry in a multiprocessor system by replacing one (or more) processors with a bypass or pass-through device. Using the pass-through mechanism, the reduced number of processors in the system enables all of the remaining processors to connect to each other directly using the interconnect links. The reduction in processor count improves symmetry and reduces overall latency thereby potentially improving performance of certain applications despite having fewer processors. In one specific implementation, the pass through device is used to connect two HyperTransport links together where each of the links is connected to a processor at the other end.
Inventors
- 👤 John Howard Barker
- 👤 Beeman Noel Fallwell, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:41
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/22; H05K3/222; H05K2201/00; H05K2201/10; H05K2201/10227; H05K2201/10325
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
113 words
A multiprocessor system, comprising: a set of processors; a system board having a set of sockets, each socket suitable for receiving one of the set of processors wherein the number of sockets in the set of sockets exceeds the number of processors in the set of processors; a set of interconnects providing point-to-point links between at least some of the sockets; and a pass through device occupying one of the set of sockets, wherein the pass through device connects a first interconnect link connected to the socket and a second interconnect link connected to the socket such that the first and second interconnect links form the functional equivalent of a single interconnect link.
Claim 2
Dependent Claim
113 words
A multiprocessor system, comprising: a set of processors; a system board having a set of sockets, each socket suitable for receiving one of the set of processors wherein the number of sockets in the set of sockets exceeds the number of processors in the set of processors; a set of interconnects providing point-to-point links between at least some of the sockets; and a pass through device occupying one of the set of sockets, wherein the pass through device connects a first interconnect link connected to the socket and a second interconnect link connected to the socket such that the first and second interconnect links form the functional equivalent of a single interconnect link.
Claim 3
Dependent Claim
33 words
The system of claim 1 , wherein the system includes a local system memory corresponding to each processor, wherein the local memory of each processor is accessible to each of the other processors.
Claim 4
Dependent Claim
52 words
The system of claim 2 , wherein the system is characterized by a two tiered memory latency wherein memory accesses to a processor's local memory is characterized by a first memory access latency while memory accesses to the system memory of any other processor are characterized by a second memory access latency.
Claim 5
Dependent Claim
25 words
The system of claim 1 , wherein the number of sockets in the set of sockets exceeds the number of processors by at least one.
Claim 6
Dependent Claim
25 words
The system of claim 1 , wherein the point-to-point links consist of power signals, ground signals, and a set of uni-directional data and command signals.
Claim 7
Dependent Claim
16 words
The system of claim 5 , wherein the point-to-point links are further characterized as HyperTransport links.
Claim 8
Dependent Claim
35 words
The system of claim 1 , wherein the set of processors include a first processor connected via corresponding instances of the point-to-point link to an I/O bridge, a second processor, and the pass through device.
Claim 9
Dependent Claim
33 words
The system of claim 7 , wherein the set of processor include a second processor connected via corresponding instances of the point-to-point link to the pass through device and to a third processor.
Claim 10
Dependent Claim
25 words
The system of claim 8 , wherein the third processor is further connected to the first processor via a corresponding instance of the point-to-point link.
Claim 11
Dependent Claim
129 words
A data processing system, comprising: a system board including a set of sockets suitable for receiving a corresponding set of processors and further including a first instance of an inter-chip link connecting a first socket of the set of sockets to a second socket and a second instance of an inter-chip link connecting the second socket to a third socket; a first processor inserted in the first processor socket; a second processor inserted in the third processor socket; and a pass through device inserted in the second socket, wherein the pass through device connects the first instance of the inter-chip link to the second instance of the inter-chip wherein the first processor is directly connected to the second processor via the first and second instances of the inter-chip link.
Claim 12
Dependent Claim
129 words
A data processing system, comprising: a system board including a set of sockets suitable for receiving a corresponding set of processors and further including a first instance of an inter-chip link connecting a first socket of the set of sockets to a second socket and a second instance of an inter-chip link connecting the second socket to a third socket; a first processor inserted in the first processor socket; a second processor inserted in the third processor socket; and a pass through device inserted in the second socket, wherein the pass through device connects the first instance of the inter-chip link to the second instance of the inter-chip wherein the first processor is directly connected to the second processor via the first and second instances of the inter-chip link.
Claim 13
Dependent Claim
17 words
The system of claim 10 , wherein each instance of the inter-chip link comprises a point-to-point link.
Claim 14
Dependent Claim
16 words
The system of claim 10 , wherein the inter-chip link includes a set of uni-directional signals.
Claim 15
Dependent Claim
30 words
The system of claim 10 , wherein the first processor is directly connected to a first system memory and the second processor is directly connected to a second system memory.
Claim 16
Dependent Claim
36 words
The system of claim 10 , wherein the system board includes a set of four processor sockets and wherein three of the sockets are populated with processors and the pass through device populates a fourth socket.
Claim 17
Dependent Claim
24 words
The system of claim 10 , wherein each of the set of processors is enabled to connect to three instances of the inter-chip link.
Claim 18
Dependent Claim
25 words
The system of claim 12 , wherein the first and second instances of the inter-chip link comprise first and second instanced of a HyperTransport link.
Claim 19
Dependent Claim
53 words
The system of claim 13 , wherein the system exhibits two tiered memory access latency in which access from a processor to its corresponding system memory is characterized by a first access latency and access by any processor to a system memory of any other processor is characterized by a second access latency.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-02-27 | 2009-08-29 | 2010-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-02-27 | 2013-08-29 | 2014-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-02-27 | 2017-08-29 | 2018-02-28 | $7700.00 | Window Closed / Lapsed |