US6976239B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Methods and apparatus for implementing parameterizable processors and peripherals
Assignee: Altera Corp
•
Filing: 2001-06-12
•
Granted: 2005-12-13
•
Expires: 2021-06-12
Abstract
Abstract Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.
Inventors
- 👤 Tim Allen
- 👤 Michael Fairman
- 👤 Jeffrey Orion Pritchard
- 👤 Bryan Hoyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:15
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
98 words
A method for implementing a programmable chip, the method comprising: identifying first parameter information corresponding to a processor core, the first parameter information for configuring the processor core on the programmable chip; identifying second parameter information corresponding to a peripheral, the second parameter information for configuring the peripheral on the programmable chip; generating a logic description using the first and second parameter information, wherein the logic description provides logic information for implementing the processor core and the peripheral on the programmable chip, wherein the logic information comprises device driver logic for implementing the peripheral on the programmable chip.
Claim 2
Independent Claim
98 words
A method for implementing a programmable chip, the method comprising: identifying first parameter information corresponding to a processor core, the first parameter information for configuring the processor core on the programmable chip; identifying second parameter information corresponding to a peripheral, the second parameter information for configuring the peripheral on the programmable chip; generating a logic description using the first and second parameter information, wherein the logic description provides logic information for implementing the processor core and the peripheral on the programmable chip, wherein the logic information comprises device driver logic for implementing the peripheral on the programmable chip.
Claim 3
Dependent Claim
13 words
The method of claim 1 , wherein the peripheral is a peripheral component.
Claim 4
Dependent Claim
21 words
The method of claim 2 , wherein the peripheral component is a parameterizable peripheral component available from a library of peripherals.
Claim 5
Dependent Claim
17 words
The method of claim 3 , wherein the library of peripherals includes a plurality of parameterizable peripherals.
Claim 6
Dependent Claim
13 words
The method of claim 1 , wherein the peripheral is a peripheral interface.
Claim 7
Dependent Claim
15 words
The method of claim 5 , wherein the peripheral is an interface to off-chip memory.
Claim 8
Dependent Claim
15 words
The method of claim 1 , wherein the logic description is a synthesizable logic file.
Claim 9
Dependent Claim
14 words
The method of claim 7 , wherein the logic description is an HDL file.
Claim 10
Dependent Claim
15 words
The method of claim 1 , wherein the logic description is a synthesized logic file.
Claim 11
Dependent Claim
14 words
The method of claim 9 , wherein the logic description is an EDF file.
Claim 12
Dependent Claim
14 words
The method of claim 1 , wherein the peripheral is a custom peripheral component.
Claim 13
Dependent Claim
14 words
The method of claim 1 , wherein the peripheral is a custom peripheral interface.
Claim 14
Dependent Claim
33 words
The method of claim 1 , wherein generating the logic description using the first and second parameter in on comprises generating connector logic for allowing interconnects between the processor core and the peripheral.
Claim 15
Dependent Claim
23 words
The method of claim 1 , wherein generating connector logic comprises identifying the I/O ports associated with the processor core and the peripherals.
Claim 16
Dependent Claim
23 words
The method of claim 1 , wherein identifying first and second parameter information comprises receiving first and second parameter information through a wizard.
Claim 17
Dependent Claim
35 words
The method of claim 1 , wherein identifying first and second parameter information comprises receiving first and second parameter information through a subwizard, the subwizard spawned as a result of user interaction with the wizard.
Claim 18
Independent Claim
108 words
A system for implementing a programmable chip, the system comprising: memory; a processor coupled with memory, the processor configured to identify parameter information corresponding to a processor core, the first parameter information for configuring the processor core on the programmable chip, identify second parameter information corresponding to a peripheral, the second parameter information for configuring the peripheral on the programmable chip, and generate a logic description using the first and second parameter information, wherein the logic description provides logic information for implementing the processor core and the peripheral on the programmable chip, wherein the logic information comprises device driver logic for implementing the peripheral on the programmable chip.
Claim 19
Independent Claim
108 words
A system for implementing a programmable chip, the system comprising: memory; a processor coupled with memory, the processor configured to identify parameter information corresponding to a processor core, the first parameter information for configuring the processor core on the programmable chip, identify second parameter information corresponding to a peripheral, the second parameter information for configuring the peripheral on the programmable chip, and generate a logic description using the first and second parameter information, wherein the logic description provides logic information for implementing the processor core and the peripheral on the programmable chip, wherein the logic information comprises device driver logic for implementing the peripheral on the programmable chip.
Claim 20
Dependent Claim
13 words
The system of claim 17 , wherein the peripheral is a peripheral component.
Claim 21
Dependent Claim
13 words
The system of claim 17 , wherein the peripheral is a peripheral interface.
Claim 22
Dependent Claim
13 words
The system of claim 17 wherein the logic description is an HDL file.
Claim 23
Dependent Claim
15 words
The system of claim 17 , wherein the logic description is a synthesized logic file.
Claim 24
Dependent Claim
13 words
The system of claim 17 , wherein the peripheral is a custom peripheral.
Claim 25
Dependent Claim
112 words
A computer program product for implementing a programmable chip, the computer program product comprising: computer code for identifying first parameter information corresponding to a processor core, the first parameter information for configuring the processor core on the programmable chip; computer code for identifying second parameter information corresponding to a peripheral, the second parameter information for configuring the peripheral on the programmable chip; and computer code for generating a logic description using the first and second parameter information, wherein the logic description provides logic information for implementing the processor core and the peripheral on the programmable chip, wherein the logic information comprises device driver logic for implementing the peripheral on the programmable chip.
Claim 26
Dependent Claim
112 words
A computer program product for implementing a programmable chip, the computer program product comprising: computer code for identifying first parameter information corresponding to a processor core, the first parameter information for configuring the processor core on the programmable chip; computer code for identifying second parameter information corresponding to a peripheral, the second parameter information for configuring the peripheral on the programmable chip; and computer code for generating a logic description using the first and second parameter information, wherein the logic description provides logic information for implementing the processor core and the peripheral on the programmable chip, wherein the logic information comprises device driver logic for implementing the peripheral on the programmable chip.
Claim 27
Dependent Claim
15 words
The computer program product of claim 23 , wherein the peripheral is a peripheral component.
Claim 28
Dependent Claim
15 words
The computer program product of claim 23 , wherein the peripheral is a peripheral interface.
Claim 29
Dependent Claim
15 words
The computer program product of claim 23 wherein the logic description is an HDL file.
Claim 30
Dependent Claim
17 words
The computer program product of claim 23 , wherein the logic description is a synthesized logic file.
Claim 31
Dependent Claim
15 words
The computer program product of claim 23 , wherein the peripheral is a custom peripheral.
Claim 32
Independent Claim
104 words
A system for implementing a programmable chip, the method comprising: means for identifying fist parameter information corresponding to a processor core, the first parameter information for configuring the processor core on the programmable chip; means for identifying second parameter information corresponding to a peripheral the second parameter information for configuring the peripheral on the programmable chip; means for generating a logic description using the first and second parameter information, wherein the logic description provides logic information for implementing the processor core and the peripheral on the programmable chip, wherein the logic information comprises device driver logic for implementing the peripheral on the programmable chip.
Claim 33
Independent Claim
104 words
A system for implementing a programmable chip, the method comprising: means for identifying fist parameter information corresponding to a processor core, the first parameter information for configuring the processor core on the programmable chip; means for identifying second parameter information corresponding to a peripheral the second parameter information for configuring the peripheral on the programmable chip; means for generating a logic description using the first and second parameter information, wherein the logic description provides logic information for implementing the processor core and the peripheral on the programmable chip, wherein the logic information comprises device driver logic for implementing the peripheral on the programmable chip.
References Cited (Backward Citations)
US5841663A
Cited
US5963454A
Cited
US6460172B1
Cited
US6026226A
Cited
US6006022A
Cited
US5883814A
Cited
US6049837A
Cited
US6473783B2
Cited
US6080201A
Cited
US6345212B1
Cited
US6401230B1
Cited
US6574791B1
Cited
US6477683B1
Cited
US6594711B1
Cited
US20040015502A1
Cited
US20030093655A1
Cited
US20030120896A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-12-12 | 2009-06-13 | 2009-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-12-12 | 2013-06-13 | 2013-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-12-12 | 2017-06-13 | 2017-12-13 | $7700.00 | Window Closed / Lapsed |