Integrated placement and synthesis for timing closure of microprocessors

Claim 3

A method as in claim 1 wherein the step of placing comprises defining cuts across the image to create multiple partitions within in the image, the locations for the components being established in the image with respect to the partitions.

Claim 4

A method as in claim 2 wherein the step of synthesizing is repeated after every cut.

Claim 5

A method as in claim 2 wherein the step of synthesizing is repeated after a predetermined number of cuts.

Claim 6

A method as in claim 1 further comprising performing a transform on the circuit after the step of placing if a path in the circuit does not meet its associated timing constraints.

Claim 7

A method as in claim 1 wherein the step of generating a behavioral model comprises describing the desired circuit in a hardware description language.

Claim 8

A computer aided semiconductor circuit design system having improved timing convergence, the system comprising: means for generating behavioral model of a desired semiconductor circuit, the behavioral model including timing constraints for individual paths in the circuit; means for synthesizing the behavioral model to produce a netlist which represents an implementation of the desired semiconductor circuit mapped to a specific semiconductor technology, the netlist including a list of components in the circuit and a list of nets which connect the components in the circuit, wherein the means for synthesizing includes means for performing a timing analysis on the implementation so that the paths in the circuit represented by the netlist meet the timing constraints, the timing analysis being performed using estimated wire lengths for the nets; means for placing the components in the netlist into an image representing a predefined area of a semiconductor chip, wherein the means for the placing includes a means for determining actual wire lengths for the nets in the netlist; means for performing a timing analysis on the implementation set forth in the netlist using the actual wire lengths for the nets in the netlist; means for modifying the netlist in the event the timing analysis using the actual wire lengths indicates a violation of any of the timing constraints; means for placing the components in the modified netlist into the image representing the predefined area of the semiconductor chip, wherein the means for placing the components in the modified netlist includes means determining actual wire lengths for the nets in the modified netlist; means for performing a timing analysis on the implementation set forth in the modified netlist using the actual wire lengths for the nets in the modified netlist; means for repeating the functions of modifying the netlist, placing the components in the modified netlist, and performing the timing analysis on the implementation set forth in the modified netlist using the actual wire lengths for the nets in the modified netlist until said timing analysis on the implementation set forth in the modified netlist indicates no violation of any of the timing constraints; and means for routing the circuit represented by the modified netlist after the timing analysis on the implementation set forth in the modified netlist indicates no violation of any of the timing constraints.

Claim 9

A computer aided semiconductor circuit design system having improved timing convergence, the system comprising: means for generating behavioral model of a desired semiconductor circuit, the behavioral model including timing constraints for individual paths in the circuit; means for synthesizing the behavioral model to produce a netlist which represents an implementation of the desired semiconductor circuit mapped to a specific semiconductor technology, the netlist including a list of components in the circuit and a list of nets which connect the components in the circuit, wherein the means for synthesizing includes means for performing a timing analysis on the implementation so that the paths in the circuit represented by the netlist meet the timing constraints, the timing analysis being performed using estimated wire lengths for the nets; means for placing the components in the netlist into an image representing a predefined area of a semiconductor chip, wherein the means for the placing includes a means for determining actual wire lengths for the nets in the netlist; means for performing a timing analysis on the implementation set forth in the netlist using the actual wire lengths for the nets in the netlist; means for modifying the netlist in the event the timing analysis using the actual wire lengths indicates a violation of any of the timing constraints; means for placing the components in the modified netlist into the image representing the predefined area of the semiconductor chip, wherein the means for placing the components in the modified netlist includes means determining actual wire lengths for the nets in the modified netlist; means for performing a timing analysis on the implementation set forth in the modified netlist using the actual wire lengths for the nets in the modified netlist; means for repeating the functions of modifying the netlist, placing the components in the modified netlist, and performing the timing analysis on the implementation set forth in the modified netlist using the actual wire lengths for the nets in the modified netlist until said timing analysis on the implementation set forth in the modified netlist indicates no violation of any of the timing constraints; and means for routing the circuit represented by the modified netlist after the timing analysis on the implementation set forth in the modified netlist indicates no violation of any of the timing constraints.

Claim 10

A system as in claim 7 wherein the means for placing comprises a means for defining cuts across the image to create multiple partitions within the image so that the locations for the components are established in the image with respect to the partitions.

Claim 11

A system as in claim 8 wherein the means for substituting the actual wire lengths for the estimated wire lengths performs re-synthesis after every cut.

Claim 12

A system as in claim 8 wherein the means for substituting the actual wire lengths for the estimated wire lengths performs re-synthesis after a predetermined number of cuts.

Claim 13

A system as in claim 7 further comprising means for transforming the circuit after if a path in the circuit does not meet its associated timing constraints.

Claim 14

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for placing circuit elements in an integrated circuit image, said method steps comprising: generating behavioral model of a desired semiconductor circuit, the behavioral model including timing constraints for individual paths in the circuit; synthesizing the behavioral model to produce a netlist which represents an implementation of the desired semiconductor circuit mapped to a specific semiconductor technology, the netlist including a list of components in the circuit and a list of nets which connect the components in the circuit, the step of synthesizing including performing a timing analysis on the implementation so that the paths in the circuit represented by the netlist meet the timing constraints, the timing analysis being performed using estimated wire lengths for the nets; placing the components in the netlist into an image representing a predefined area of a semiconductor chip, the step of placing including determining actual wire lengths for the nets in the netlist; performing a timing analysis on the implementation set forth in the netlist using the actual wire lengths for the nets in the netlist; modifying the netlist in the event the timing analysis using the actual wire lengths indicates a violation of any of the timing constraints; placing the components in the modified netlist into the image representing the predefined area of the semiconductor chip, the step of placing the components in the modified netlist including determining actual wire lengths for the nets in the modified netlist; performing a timing analysis on the implementation set forth in the modified netlist using the actual wire lengths for the nets in the modified netlist; repeating the steps of modifying the netlist, placing the components in the modified netlist, and performing the timing analysis on the implementation set forth in the modified netlist using the actual wire lengths for the nets in the modified netlist until said timing analysis on the implementation set forth in the modified netlist indicates no violation of any of the timing constraints; and routing the circuit represented by the modified netlist after the timing analysis on the implementation set forth in the modified netlist indicates no violation of any of the timing constraints.

Claim 15

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for placing circuit elements in an integrated circuit image, said method steps comprising: generating behavioral model of a desired semiconductor circuit, the behavioral model including timing constraints for individual paths in the circuit; synthesizing the behavioral model to produce a netlist which represents an implementation of the desired semiconductor circuit mapped to a specific semiconductor technology, the netlist including a list of components in the circuit and a list of nets which connect the components in the circuit, the step of synthesizing including performing a timing analysis on the implementation so that the paths in the circuit represented by the netlist meet the timing constraints, the timing analysis being performed using estimated wire lengths for the nets; placing the components in the netlist into an image representing a predefined area of a semiconductor chip, the step of placing including determining actual wire lengths for the nets in the netlist; performing a timing analysis on the implementation set forth in the netlist using the actual wire lengths for the nets in the netlist; modifying the netlist in the event the timing analysis using the actual wire lengths indicates a violation of any of the timing constraints; placing the components in the modified netlist into the image representing the predefined area of the semiconductor chip, the step of placing the components in the modified netlist including determining actual wire lengths for the nets in the modified netlist; performing a timing analysis on the implementation set forth in the modified netlist using the actual wire lengths for the nets in the modified netlist; repeating the steps of modifying the netlist, placing the components in the modified netlist, and performing the timing analysis on the implementation set forth in the modified netlist using the actual wire lengths for the nets in the modified netlist until said timing analysis on the implementation set forth in the modified netlist indicates no violation of any of the timing constraints; and routing the circuit represented by the modified netlist after the timing analysis on the implementation set forth in the modified netlist indicates no violation of any of the timing constraints.