Patent US6956437B2 successfully refreshed from Google Patents.
US6956437B2
Expired / Lapsed
US
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Metal-oxide-semiconductor device having integrated bias circuit
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 2003-12-23
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Granted: 2005-10-18
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Expires: 2023-12-23
Abstract
Abstract An IC device includes an MOS device having a gate terminal, a source terminal and a drain terminal, the gate terminal being operatively coupled to an input of the IC device, the drain terminal being operatively coupled to an output of the IC device, and the source terminal being coupled to a negative voltage supply. The IC device further includes a bias generator operatively coupled to the gate terminal of the MOS device, the bias generator generating a bias voltage and/or a bias current for biasing the MOS device at a substantially constant quiescent operating point. The bias generator is configured such that the bias voltage and/or bias current varies as a function of a junction temperature of the MOS device. In this manner, the bias generator accurately tracks one or more operating conditions of the MOS device, thereby improving the performance of the device.
Inventors
- 👤 Osvaldo Jorge Lopez
- 👤 Joel Morrison Lott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:35
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/189; H03F3/19; H03F3/195; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; H03F1/00; H03F1/30; H03F1/301; H03F2200/00; H03F2200/18; H03F2200/451; H10; H10W; H10W72/00; H10W72/50; H10W72/541; H10W72/5445
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
173 words
A packaged power transistor integrated circuit (IC) device, comprising: a metal-oxide-semiconductor (MOS) transistor device including a gate terminal, a source terminal and a drain terminal, the gate terminal being operatively coupled to a first package lead of the IC device, the drain terminal being operatively coupled to a second package lead of the IC device, and the source terminal being adapted for connection to a negative voltage supply; and a bias generator operatively coupled to the gate terminal of the MOS device, the bias generator generating a bias output for biasing the MOS device at a substantially constant quiescent operating point, the bias generator being configured such that the bias output varies as a function of a junction temperature of the MOS device; wherein the IC device is configured to receive both an input radio frequency (RF) signal and a substantially direct current (DC) reference source signal on the first package lead, the bias generator being adapted to receive the reference source signal and to generate the bias output as a function thereof.
Claim 2
Dependent Claim
173 words
A packaged power transistor integrated circuit (IC) device, comprising: a metal-oxide-semiconductor (MOS) transistor device including a gate terminal, a source terminal and a drain terminal, the gate terminal being operatively coupled to a first package lead of the IC device, the drain terminal being operatively coupled to a second package lead of the IC device, and the source terminal being adapted for connection to a negative voltage supply; and a bias generator operatively coupled to the gate terminal of the MOS device, the bias generator generating a bias output for biasing the MOS device at a substantially constant quiescent operating point, the bias generator being configured such that the bias output varies as a function of a junction temperature of the MOS device; wherein the IC device is configured to receive both an input radio frequency (RF) signal and a substantially direct current (DC) reference source signal on the first package lead, the bias generator being adapted to receive the reference source signal and to generate the bias output as a function thereof.
Claim 3
Dependent Claim
76 words
The IC device of claim 1 , wherein the bias generator comprises a current mirror operatively coupled to the MOS transistor device, the current mirror generating a reference current that is substantially matched to a percentage of a quiescent current in the MOS transistor device, the bias generator being configured to adjust the bias output such that the reference current is substantially constant over variations in one or more operating conditions of the MOS transistor device.
Claim 4
Dependent Claim
60 words
The IC device of claim 1 , wherein the bias generator comprises a reference transistor operatively coupled to the MOS transistor device, the reference transistor and the MOS transistor device being configured in a current mirror arrangement, wherein a ratio of a reference current in the reference transistor and a quiescent current in the MOS transistor device is substantially constant.
Claim 5
Dependent Claim
51 words
The IC device of claim 3 , wherein the bias generator further comprises a current source operatively coupled to the reference transistor, the current source being configured to generate the reference current, the bias generator being operative to vary the bias output so as to maintain a substantially constant reference current.
Claim 6
Dependent Claim
174 words
The IC device of claim 1 , wherein the bias generator comprises: a second transistor including gate, source and drain terminals, the gate and source terminals of the second transistor being connected to the gate and source terminals, respectively, of the MOS transistor device, and the drain terminal of the second transistor being connected to a substantially constant current source; and a third transistor including gate, source and drain terminals, the gate terminal of the third transistor being connected to the drain terminal of the second transistor, the source terminal of the third transistor being connected to the gate terminal of the second transistor, and the drain terminal of the third transistor being connected to a positive voltage supply, the third transistor being configured to supply the bias output at the gate terminals of the second transistor and MOS transistor device and adjusting the bias output accordingly so as to maintain a substantially constant quiescent current in the MOS transistor device over variations in one or more operating conditions of the MOS transistor device.
Claim 7
Dependent Claim
64 words
The IC device of claim 1 , further comprising at least one of: an input impedance matching circuit operatively coupled between the first package lead of the IC device and the gate terminal of the MOS transistor device; and an output impedance matching circuit operatively coupled between the drain terminal of the MOS transistor device and the second package lead of the IC device.
Claim 8
Dependent Claim
52 words
The IC device of claim 1 , further comprising a filter circuit coupled between the bias generator and the gate terminal of the MOS transistor device, the filter circuit being configurable for substantially removing frequency components above a desired cutoff frequency potentially present in the bias output generated by the bias generator.
Claim 9
Dependent Claim
52 words
The IC device of claim 1 , wherein the bias generator includes an input for receiving at least one of a reference voltage and reference current, the bias generator controlling a quiescent current in the MOS transistor device in response to the at least one of the reference voltage and reference current.
Claim 10
Dependent Claim
28 words
The IC device of claim 8 , wherein the at least one of the reference voltage and reference current is generated externally in relation to the IC device.
Claim 11
Dependent Claim
28 words
The IC device of claim 8 , wherein the at least one of the reference voltage and reference current is generated internally in relation to the IC device.
Claim 12
Dependent Claim
23 words
The IC device of claim 1 , wherein the MOS transistor device is formed on a same semiconductor die as the bias generator.
Claim 13
Dependent Claim
22 words
The IC device of claim 1 , wherein the bias generator is formed in close relative proximity to the MOS transistor device.
Claim 14
Dependent Claim
18 words
The IC device of claim 1 , wherein the MOS transistor device is a lateral drain MOS device.
Claim 15
Dependent Claim
23 words
The IC device of claim 1 , wherein the bias output comprises at least one of a bias voltage and a bias current.
Claim 16
Independent Claim
133 words
A method for forming a discrete transistor device having a substantially constant quiescent operating point, the method comprising the steps of: detecting a junction temperature of the transistor device; generating a bias output for biasing the transistor device at a quiescent operating point, the bias output being a function of a substantially direct current (DC) reference signal supplied to the transistor device; and varying the bias output as a function of the detected junction temperature of the transistor device so as to maintain a substantially constant quiescent operating point in the transistor device over variations in one or more operating conditions of the transistor device; wherein the DC reference signal and an input radio frequency (RF) signal received by the transistor device are supplied on a same package lead of the transistor device.
Claim 17
Independent Claim
133 words
A method for forming a discrete transistor device having a substantially constant quiescent operating point, the method comprising the steps of: detecting a junction temperature of the transistor device; generating a bias output for biasing the transistor device at a quiescent operating point, the bias output being a function of a substantially direct current (DC) reference signal supplied to the transistor device; and varying the bias output as a function of the detected junction temperature of the transistor device so as to maintain a substantially constant quiescent operating point in the transistor device over variations in one or more operating conditions of the transistor device; wherein the DC reference signal and an input radio frequency (RF) signal received by the transistor device are supplied on a same package lead of the transistor device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2008-10-17 | 2009-04-18 | 2009-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-10-17 | 2013-04-18 | 2013-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-10-17 | 2017-04-18 | 2017-10-18 | $7700.00 | Window Closed / Lapsed |