US6941532B2 — Clock skew verification methodology for grid-base…

Claim 1

Independent Claim 118 words

A method of determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the method comprising: partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; simulating each of the plurality of local clock nets to generate a load for each of the plurality of local clock nets on the global clock net, said simulating including measuring clock arrival time and slope at each point where a clock element is connected; simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; and combining the plurality of simulations to form a complete clock net simulation.

Claim 2

Independent Claim 118 words

A method of determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the method comprising: partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; simulating each of the plurality of local clock nets to generate a load for each of the plurality of local clock nets on the global clock net, said simulating including measuring clock arrival time and slope at each point where a clock element is connected; simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; and combining the plurality of simulations to form a complete clock net simulation.

Claim 3

Dependent Claim 25 words

The method as defined in claim 1 , wherein partitioning comprises breaking the complete clock net into a plurality of parts approximating rectangular grid coordinates.

Claim 4

Dependent Claim 29 words

The method as defined in claim 1 , further comprising breaking at least one of the plurality of local clock nets down into at least one sub-local clock net.

Claim 5

Dependent Claim 26 words

The method as defined in claim 3 , further comprising simulating the at least one sub-local clock net prior to simulating the corresponding local clock net.

Claim 6

Dependent Claim 23 words

The method as defined in claim 1 , wherein at least two of the plurality of local clock nets are simulated in parallel.

Claim 7

Dependent Claim 86 words

The method as defined in claim 1 , wherein simulating each of the plurality of local clock nets comprises: extracting a layout of the local clock net and the conductors routed above and through the local clock net from a microprocessor network database; extracting component values of the elements of the local clock net from the microprocessor network database; simulating the local clock net based on the layout and the component values; and extracting a load of the local clock net on the global clock net.

Claim 8

Dependent Claim 44 words

The method as defined in claim 6 , wherein simulating the local clock net comprises assuming that the clock arrival times from the global clock net will be simultaneous at all points where the local clock net is connected to the global clock net.

Claim 9

Dependent Claim 75 words

The method as defined in claim 1 , wherein simulating the global clock net comprises: extracting the layout of the global clock net from a microprocessor network database; extracting component values of the elements of the global clock net from the microprocessor network database; inserting the simulated loads of the plurality of local clock nets; and simulating the global clock net based on the layout, the component values, and the simulated local clock net loads.

Claim 10

Dependent Claim 21 words

The method as defined in claim 1 , further comprising storing the plurality of simulation results in a Clock Data Model.

Claim 11

Dependent Claim 21 words

The method as defined in claim 1 , further comprising evaluating the complete clock net to determine whether the results converge.

Claim 12

Dependent Claim 96 words

The method as defined in claim 10 , wherein, if the results do not converge, the method further comprises: assuming that clock arrival times are those calculated for the simulated global clock net; re-simulating at least one of the plurality of local clock nets to generate a load for the at least one local clock net on the global clock net; re-simulating the global clock net based in part on the simulated or re-simulated load of each of the plurality of local clock nets; and combining the simulations and re-simulations to form the complete clock net.

Claim 13

Dependent Claim 59 words

The method as defined in claim 11 , wherein re-simulating at least one of the plurality of local clock nets comprises: re-simulating the at least one local clock net based on the layout, the component values, and the calculated clock arrival times; and extracting a load of the at least one local clock net on the global clock net.

Claim 14

Dependent Claim 32 words

The method as defined in claim 12 , further comprising re-simulating at least a second of the plurality of local clock nets in parallel with the at least one local clock net.

Claim 15

Dependent Claim 50 words

The method as defined in claim 11 , wherein re-simulating the global clock net comprises: inserting the simulated or re-simulated loads of the plurality of local clock nets; and re-simulating the global clock net based on the layout, the component values, and the simulated or re-simulated local clock net loads.

Claim 16

Dependent Claim 23 words

The method as defined in claim 11 , further comprising storing the plurality of simulation and re-simulation results in a Clock Data Model.

Claim 17

Independent Claim 130 words

An apparatus for determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the apparatus comprising: means for partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; means for simulating each of the plurality of local clock nets to generate a load for each of the plurality of local clock nets on the global clock net, said means for simulating including means for measuring clock arrival time and slope at each point where a clock element is connected; means for simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; and means for combining the plurality of simulations to form a complete clock net simulation.

Claim 18

Independent Claim 130 words

An apparatus for determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the apparatus comprising: means for partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; means for simulating each of the plurality of local clock nets to generate a load for each of the plurality of local clock nets on the global clock net, said means for simulating including means for measuring clock arrival time and slope at each point where a clock element is connected; means for simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; and means for combining the plurality of simulations to form a complete clock net simulation.

Claim 19

Dependent Claim 29 words

The apparatus as defined in claim 16 , wherein means for partitioning comprises means for breaking the complete clock net into a plurality of parts approximating rectangular grid coordinates.

Claim 20

Dependent Claim 31 words

The apparatus as defined in claim 16 , further comprising means for breaking at least one of the plurality of local clock nets down into at least one sub-local clock net.

Claim 21

Dependent Claim 28 words

The apparatus as defined in claim 18 , further comprising means for simulating the at least one sub-local clock net prior to simulating the corresponding local clock net.

Claim 22

Dependent Claim 23 words

The apparatus as defined in claim 16 , wherein at least two of the plurality of local clock nets are simulated in parallel.

Claim 23

Dependent Claim 96 words

The apparatus as defined in claim 16 , wherein means for simulating each of the plurality of local clock nets comprises: means for extracting a layout of the local clock net and the conductors routed above and through the local clock net from a microprocessor network database; means for extracting component values of the elements of the local clock net from the microprocessor network database; means for simulating the local clock net based on the layout and the component values; and means for extracting a load of the local clock net on the global clock net.

Claim 24

Dependent Claim 48 words

The apparatus as defined in claim 21 , wherein means for simulating the local clock net comprises means for assuming that the clock arrival times from the global clock net will be simultaneous at all points where the local clock net is connected to the global clock net.

Claim 25

Dependent Claim 85 words

The apparatus as defined in claim 16 , wherein means for simulating the global clock net comprises: means for extracting the layout of the global clock net from a microprocessor network database; means for extracting component values of the elements of the global clock net from the microprocessor network database; means for inserting the simulated loads of the plurality of local clock nets; and means for simulating the global clock net based on the layout, the component values, and the simulated local clock net loads.

Claim 26

Dependent Claim 23 words

The apparatus as defined in claim 16 , further comprising means for storing the plurality of simulation results in a Clock Data Model.

Claim 27

Dependent Claim 23 words

The apparatus as defined in claim 16 , further comprising means for evaluating the complete clock net to determine whether the results converge.

Claim 28

Dependent Claim 98 words

The apparatus as defined in claim 25 , wherein the apparatus further comprises: means for assuming that clock arrival times are those calculated for the simulated global clock net; means for re-simulating at least one of the plurality of local clock nets to generate a load for the at least one local clock net on the global clock net; means for re-simulating the global clock net based in part on the simulated or re-simulated load of each of the plurality of local clock nets; and means for combining the simulations and re-simulations to form the complete clock net.

Claim 29

Dependent Claim 65 words

The apparatus as defined in claim 26 , wherein means for re-simulating at least one of the plurality of local clock nets comprises: means for re-simulating the at least one local clock net based on the layout, the component values, and the calculated clock arrival times; and means for extracting a load of the at least one local clock net on the global clock net.

Claim 30

Dependent Claim 34 words

The apparatus as defined in claim 27 , further comprising means for re-simulating at least a second of the plurality of local clock nets in parallel with the at least one local clock net.

Claim 31

Dependent Claim 56 words

The apparatus as defined in claim 26 , wherein means for re-simulating the global clock net comprises: means for inserting the simulated or re-simulated loads of the plurality of local clock nets; and means for re-simulating the global clock net based on the layout, the component values, and the simulated or re-simulated local clock net loads.

Claim 32

Dependent Claim 25 words

The apparatus as defined in claim 26 , further comprising means for storing the plurality of simulation and re-simulation results in a Clock Data Model.

Claim 33

Independent Claim 149 words

An apparatus for determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the apparatus comprising: a partitioner for horizontally and vertically partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; at least one local clock net simulator for simulating at least one of the plurality of local clock nets to generate a load for the at least one local clock net on the global clock net, said local net simulator including a clock monitor for measuring clock arrival time and slope at each point where a clock element is connected; a global clock net simulator for simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; and a merging unit for combining the plurality of simulations to form a complete clock net simulation.

Claim 34

Independent Claim 149 words

An apparatus for determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the apparatus comprising: a partitioner for horizontally and vertically partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; at least one local clock net simulator for simulating at least one of the plurality of local clock nets to generate a load for the at least one local clock net on the global clock net, said local net simulator including a clock monitor for measuring clock arrival time and slope at each point where a clock element is connected; a global clock net simulator for simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; and a merging unit for combining the plurality of simulations to form a complete clock net simulation.

Claim 35

Dependent Claim 29 words

The apparatus as defined in claim 31 , wherein the partitioner comprises a cutter for breaking the complete clock net into a plurality of parts approximating rectangular grid coordinates.

Claim 36

Dependent Claim 31 words

The apparatus as defined in claim 31 , wherein the partitioner vertically sub-partitions at least one of the plurality of local clock nets down into at least one sub-local clock net.

Claim 37

Dependent Claim 33 words

The apparatus as defined in claim 33 , wherein the at least one local clock net simulator simulates the at least one sub-local clock net prior to simulating the corresponding local clock net.

Claim 38

Dependent Claim 42 words

The apparatus as defined in claim 31 , further comprising at least a second local clock net simulator wherein at least a second of the plurality of local clock nets is simulated in parallel with the at least one local clock net.

Claim 39

Dependent Claim 104 words

The apparatus as defined in claim 31 , wherein the at least one local clock net simulator comprises: a layout extractor for extracting a layout of the local clock net and the conductors routed above and through the local clock net from a microprocessor network database; a component value extractor for extracting component values of the elements of the local clock net from the microprocessor network database; a local clock net simulator for simulating the local clock net based on the layout and the component values; and a load extractor for extracting a load of the local clock net on the global clock net.

Claim 40

Dependent Claim 46 words

The apparatus as defined in claim 36 , wherein the local clock net simulator assumes for the simulation that the clock arrival times from the global clock net will be simultaneous at all points where the local clock net is connected to the global clock net.

Claim 41

Dependent Claim 114 words

The apparatus as defined in claim 31 , wherein the global clock net simulator comprises: a layout extractor for extracting the layout of the global clock net from a microprocessor network database; a component extractor for extracting component values of the elements of the global clock net from the microprocessor network database; a load insertion unit for inserting the simulated loads of the plurality of local clock nets; and a simulator for simulating the global clock net based on the layout, the component values, and the simulated local clock net loads. 39 .m The apparatus as defined in claim 31 , further comprising a Clock Data Model for storing the plurality of simulation results.

Claim 42

Dependent Claim 25 words

The apparatus as defined in claim 31 , further comprising a convergence evaluator for evaluating the complete clock net to determine whether the results converge.

Claim 43

Dependent Claim 112 words

The apparatus as defined in claim 40 , wherein, when the results are found not to converge: the apparatus assumes that clock arrival times are those calculated for the simulated global clock net; the at least one local clock net simulator re-simulates at least one of the plurality of local clock nets to generate a load for the at least one local clock net on the global clock net; the global clock net simulator re-simulates the global clock net based in part on the simulated or re-simulated load of each of the plurality of local clock nets; and the merging unit combines the simulations and re-simulations to form the complete clock net.

Claim 44

Dependent Claim 23 words

The apparatus as defined in claim 41 , further comprising a Clock Data Model for storing the plurality of simulation and re-simulation results.

Claim 45

Dependent Claim 128 words

A computer-readable medium having stored thereon computer-executable instructions for performing a method of determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the method comprising: partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; simulating each of the plurality of local clock nets to generate a load for each of the plurality of local clock nets on the global clock net, said simulating including measuring clock arrival time and slope at each point where a clock element is connected; simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; and combining the plurality of simulations to form a complete clock net simulation.

Claim 46

Dependent Claim 128 words

A computer-readable medium having stored thereon computer-executable instructions for performing a method of determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the method comprising: partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; simulating each of the plurality of local clock nets to generate a load for each of the plurality of local clock nets on the global clock net, said simulating including measuring clock arrival time and slope at each point where a clock element is connected; simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; and combining the plurality of simulations to form a complete clock net simulation.

Claim 47

Dependent Claim 26 words

The computer-readable medium as defined in claim 43 , wherein partitioning comprises breaking the complete clock net into a plurality of parts approximating rectangular grid coordinates.

Claim 48

Dependent Claim 33 words

The computer-readable medium as defined in claim 43 , wherein the method further comprises breaking at least one of the plurality of local clock nets down into at least one sub-local clock net.

Claim 49

Dependent Claim 30 words

The computer-readable medium as defined in claim 45 , wherein the method further comprises simulating the at least one sub-local clock net prior to simulating the corresponding local clock net.

Claim 50

Dependent Claim 24 words

The computer-readable medium as defined in claim 43 , wherein at least two of the plurality of local clock nets are simulated in parallel.

Claim 51

Dependent Claim 87 words

The computer-readable medium as defined in claim 43 , wherein simulating each of the plurality of local clock nets comprises: extracting a layout of the local clock net and the conductors routed above and through the local clock net from a microprocessor network database; extracting component values of the elements of the local clock net from the microprocessor network database; simulating the local clock net based on the layout and the component values; and extracting a load of the local clock net on the global clock net.

Claim 52

Dependent Claim 45 words

The computer-readable medium as defined in claim 48 , wherein simulating the local clock net comprises assuming that the clock arrival times from the global clock net will be simultaneous at all points where the local clock net is connected to the global clock net.

Claim 53

Dependent Claim 76 words

The computer-readable medium as defined in claim 43 , wherein simulating the global clock net comprises: extracting the layout of the global clock net from a microprocessor network database; extracting component values of the elements of the global clock net from the microprocessor network database; inserting the simulated loads of the plurality of local clock nets; and simulating the global clock net based on the layout, the component values, and the simulated local clock net loads.

Claim 54

Dependent Claim 25 words

The computer-readable medium as defined in claim 43 , wherein the method further comprises storing the plurality of simulation results in a Clock Data Model.

Claim 55

Dependent Claim 25 words

The computer-readable medium as defined in claim 43 , wherein the method further comprises evaluating the complete clock net to determine whether the results converge.

Claim 56

Dependent Claim 97 words

The computer-readable medium as defined in claim 52 , wherein, if the results do not converge, the method further comprises: assuming that clock arrival times are those calculated for the simulated global clock net; re-simulating at least one of the plurality of local clock nets to generate a load for the at least one local clock net on the global clock net; re-simulating the global clock net based in part on the simulated or re-simulated load of each of the plurality of local clock nets; and combining the simulations and re-simulations to form the complete clock net.

Claim 57

Dependent Claim 60 words

The computer-readable medium as defined in claim 53 , wherein re-simulating at least one of the plurality of local clock nets comprises: re-simulating the at least one local clock net based on the layout, the component values, and the calculated clock arrival times; and extracting a load of the at least one local clock net on the global clock net.

Claim 58

Dependent Claim 36 words

The computer-readable medium as defined in claim 54 , wherein the method further comprises re-simulating at least a second of the plurality of local clock nets in parallel with the at least one local clock net.

Claim 59

Dependent Claim 51 words

The computer-readable medium as defined in claim 53 , wherein re-simulating the global clock net comprises: inserting the simulated or re-simulated loads of the plurality of local clock nets; and re-simulating the global clock net based on the layout, the component values, and the simulated or re-simulated local clock net loads.

Claim 60

Dependent Claim 27 words

The computer-readable medium as defined in claim 53 , wherein the method further comprises storing the plurality of simulation and re-simulation results in a Clock Data Model.

Claim 61

Independent Claim 136 words

A method of determining and analyzing clock insertion delays for a microprocessor design having a grid-based clock distribution net, the method comprising: partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; simulating each of the plurality of local clock nets to generate a load for each of the plurality of local clock nets on the global clock net, said simulating including measuring clock arrival time and slope at each point where a clock element is connected; simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; combining the plurality of simulations to form a complete clock net simulation; and analyzing the complete clock net to predict the clock skew for a given data transfer path.

Claim 62

Independent Claim 136 words

A method of determining and analyzing clock insertion delays for a microprocessor design having a grid-based clock distribution net, the method comprising: partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; simulating each of the plurality of local clock nets to generate a load for each of the plurality of local clock nets on the global clock net, said simulating including measuring clock arrival time and slope at each point where a clock element is connected; simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; combining the plurality of simulations to form a complete clock net simulation; and analyzing the complete clock net to predict the clock skew for a given data transfer path.

Claim 63

Dependent Claim 40 words

The method as defined in claim 58 , wherein analyzing comprises: adjusting an insertion delay of the involved elements of the given data transfer path; and re-simulating at least one local clock net involved in the given data transfer path.

Claim 64

Dependent Claim 43 words

The method as defined in claim 59 , further comprising, when the at least one re-simulated local clock net is connected to at least one sub-local clock net, evaluating the clock arrival times to determine whether the sub-local clock net should be re-simulated.

Claim 65

Dependent Claim 42 words

The method as defined in claim 59 , further comprising evaluating the at least one re-simulated local clock net load to determine whether at least one higher clock net connected to the at least one re-simulated local clock net should be re-simulated.

Claim 66

Dependent Claim 23 words

The method as defined in claim 59 , further comprising storing the plurality of simulation and re-simulation results in a Clock Data Model.

Claim 67

Independent Claim 144 words

An apparatus for determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the apparatus comprising: means for partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; means for simulating each of the plurality of local clock nets to generate a load for each of the plurality of local clock nets on the global clock net, said simulating including measuring clock arrival time and slope at each point where a clock element is connected; means for simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; means for combining the plurality of simulations to form a complete clock net simulation; and means for analyzing the complete clock net to predict the clock skew for a given data transfer path.

Claim 68

Independent Claim 144 words

An apparatus for determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the apparatus comprising: means for partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; means for simulating each of the plurality of local clock nets to generate a load for each of the plurality of local clock nets on the global clock net, said simulating including measuring clock arrival time and slope at each point where a clock element is connected; means for simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; means for combining the plurality of simulations to form a complete clock net simulation; and means for analyzing the complete clock net to predict the clock skew for a given data transfer path.

Claim 69

Dependent Claim 46 words

The apparatus as defined in claim 63 , wherein means for analyzing comprises: means for adjusting an insertion delay of the involved elements of the given data transfer path; and means for re-simulating at least one local clock net involved in the given data transfer path.

Claim 70

Dependent Claim 45 words

The apparatus as defined in claim 64 , further comprising, when the at least one re-simulated local clock net is connected to at least one sub-local clock net, means for evaluating the clock arrival times to determine whether the sub-local clock net should be re-simulated.

Claim 71

Dependent Claim 44 words

The apparatus as defined in claim 64 , further comprising means for evaluating the at least one re-simulated local clock net load to determine whether at least one higher clock net connected to the at least one re-simulated local clock net should be re-simulated.

Claim 72

Dependent Claim 25 words

The apparatus as defined in claim 64 , further comprising means for storing the plurality of simulation and re-simulation results in a Clock Data Model.

Claim 73

Independent Claim 162 words

An apparatus for determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the apparatus comprising: a partitioner for horizontally and vertically partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; at least one local clock net simulator for simulating at least one of the plurality of local clock nets to generate a load for the at least one local clock net on the global clock net, said simulating including measuring clock arrival time and slope at each point where a clock element is connected; a global clock net simulator for simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; a merging unit for combining the plurality of simulations to form a complete clock net simulation; and an analyzer for analyzing the complete clock net to predict the clock skew for a given data transfer path.

Claim 74

Independent Claim 162 words

An apparatus for determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the apparatus comprising: a partitioner for horizontally and vertically partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; at least one local clock net simulator for simulating at least one of the plurality of local clock nets to generate a load for the at least one local clock net on the global clock net, said simulating including measuring clock arrival time and slope at each point where a clock element is connected; a global clock net simulator for simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; a merging unit for combining the plurality of simulations to form a complete clock net simulation; and an analyzer for analyzing the complete clock net to predict the clock skew for a given data transfer path.

Claim 75

Dependent Claim 53 words

The apparatus as defined in claim 68 , wherein the analyzer comprises a redesign unit for adjusting an insertion delay of the involved elements of the given data transfer path, wherein the at least one local clock net simulator re-simulates at least one local clock net involved in the given data transfer path.

Claim 76

Dependent Claim 49 words

The apparatus as defined in claim 69 , further comprising, when the at least one re-simulated local clock net is connected to at least one sub-local clock net, a clock arrival time evaluator for evaluating the clock arrival times to determine whether the sub-local clock net should be re-simulated.

Claim 77

Dependent Claim 46 words

The apparatus as defined in claim 69 , further comprising a load evaluator for evaluating the at least one re-simulated local clock net load to determine whether at least one higher clock net connected to the at least one re-simulated local clock net should be re-simulated.

Claim 78

Dependent Claim 23 words

The apparatus as defined in claim 69 , further comprising a Clock Data Model for storing the plurality of simulation and re-simulation results.

Claim 79

Dependent Claim 144 words

A computer-readable medium having stored thereon computer-executable instructions for performing a method of determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the method comprising: partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; simulating each of the plurality of local clock nets to generate a load for each of the plurality of local clock nets on the global clock net, said simulating including measuring clock arrival time and slope at each point where a clock element is connected; simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; combining the plurality of simulations to form a complete clock net simulation; and analyzing the complete clock net to predict the clock skew for a given data transfer path.

Claim 80

Dependent Claim 144 words

A computer-readable medium having stored thereon computer-executable instructions for performing a method of determining clock insertion delays for a microprocessor design having a grid-based clock distribution net, the method comprising: partitioning the complete grid-based clock distribution net into a global clock net and a plurality of local clock nets; simulating each of the plurality of local clock nets to generate a load for each of the plurality of local clock nets on the global clock net, said simulating including measuring clock arrival time and slope at each point where a clock element is connected; simulating the global clock net based in part on the simulated load of each of the plurality of local clock nets; combining the plurality of simulations to form a complete clock net simulation; and analyzing the complete clock net to predict the clock skew for a given data transfer path.

Claim 81

Dependent Claim 41 words

The computer-readable medium as defined in claim 73 , wherein analyzing comprises: adjusting an insertion delay of the involved elements of the given data transfer path; and re-simulating at least one local clock net involved in the given data transfer path.

Claim 82

Dependent Claim 47 words

The computer-readable medium as defined in claim 74 , wherein the method further comprises, when the at least one re-simulated local clock net is connected to at least one sub-local clock net, evaluating the clock arrival times to determine whether the sub-local clock net should be re-simulated.

Claim 83

Dependent Claim 46 words

The computer-readable medium as defined in claim 74 , wherein the method further comprises evaluating the at least one re-simulated local clock net load to determine whether at least one higher clock net connected to the at least one re-simulated local clock net should be re-simulated.

Claim 84

Dependent Claim 27 words

The computer-readable medium as defined in claim 74 , wherein the method further comprises storing the plurality of simulation and re-simulation results in a Clock Data Model.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2008-09-05	2009-03-07	2009-09-06	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2012-09-05	2013-03-07	2013-09-06	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2016-09-05	2017-03-07	2017-09-06	$7700.00	Window Closed / Lapsed

Clock skew verification methodology for grid-based design

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