US6150865A
Expired / Lapsed
US
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Method for the positioning/routing of a global clock circuit on an integrated circuit, and associated devices
Assignee: STMicroelectronics SA
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Filing: 1999-07-09
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Granted: 2000-11-21
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Expires: 2019-07-09
Abstract
Abstract A method for positioning/routing a clock circuit for an integrated circuit compensates for phase differences by adjusting secondary amplifiers having adjustable input delays. The method includes the steps of positioning first conductive lines parallel to a first direction evenly spaced with respect to the second direction. The first conductive lines are connected to outputs of the first amplifiers. A balanced tree-like structure provides each of the first amplifiers a clock signal coming from a single source. The method further includes the steps of positioning functional blocks for forming the integrated circuit, and the positioning of second lines parallel to the second direction. Each secondary amplifier is routed to the closest second line. An equivalent electrical diagram corresponding to the path taken by the clock signal between the input of the tree-like structure device and the input of each secondary amplifier is determined. The analog simulation of the equivalent electrical diagram and the measurement of the phase delays at the input of each secondary amplifier are performed. The input delay of each secondary amplifier is then adjusted to correspond to the largest measured phase delay.
Inventors
- 👤 Steven Fluxman
- 👤 Trevor Monk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:09
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F30/00; G06F30/30; G06F30/39; G06F30/394; G06F30/396
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
197 words
A method for positioning/routing a global clock circuit on an integrated circuit, the method comprising the steps of: positioning a plurality of first conductive lines on the integrated circuit parallel to a first direction, each first conductive line being connected to at least one first amplifier having an input receiving a clock signal, the clock signal originating from a single source for forming a balanced tree-like structure with the at least one first amplifier; positioning functional blocks forming the integrated circuit and positioning a plurality of second conductive lines on the integrated circuit parallel to a second direction, each second conductive line connected to a functional block; positioning in each functional block at least one second amplifier having an adjustable input delay, and routing a closest one of the plurality of second conductive lines to each second amplifier; determining an equivalent electrical diagram corresponding to a clock signal path between an input of the tree-like structure and an input of each second amplifier; simulating the equivalent electrical diagram and measuring a phase delay at the input of each second amplifier; and adjusting the input delay of each second amplifier to correspond to a largest measured phase delay.
Claim 2
Independent Claim
197 words
A method for positioning/routing a global clock circuit on an integrated circuit, the method comprising the steps of: positioning a plurality of first conductive lines on the integrated circuit parallel to a first direction, each first conductive line being connected to at least one first amplifier having an input receiving a clock signal, the clock signal originating from a single source for forming a balanced tree-like structure with the at least one first amplifier; positioning functional blocks forming the integrated circuit and positioning a plurality of second conductive lines on the integrated circuit parallel to a second direction, each second conductive line connected to a functional block; positioning in each functional block at least one second amplifier having an adjustable input delay, and routing a closest one of the plurality of second conductive lines to each second amplifier; determining an equivalent electrical diagram corresponding to a clock signal path between an input of the tree-like structure and an input of each second amplifier; simulating the equivalent electrical diagram and measuring a phase delay at the input of each second amplifier; and adjusting the input delay of each second amplifier to correspond to a largest measured phase delay.
Claim 3
Dependent Claim
75 words
A method according to claim 1, further comprising the steps of: positioning a plurality of devices in each functional block for receiving the clock signal; arranging the plurality of devices by proximity group, each proximity groups having at least one device less than or equal to a maximum number and being positioned over a surface area less than or equal to a maximum surface area; and positioning each second amplifier within a respective proximity group.
Claim 4
Dependent Claim
26 words
A method according to claim 2, further comprising the step of balancing the proximity groups with respect to a surface area of a corresponding functional block.
Claim 5
Dependent Claim
39 words
A method according to claim 2, wherein each second amplifier comprises an output transistor; the method further comprising the step of sizing each output transistor as a function of the at least one device within each corresponding proximity group.
Claim 6
Dependent Claim
27 words
A method according to claim 2, wherein the step of positioning each second amplifier comprises positioning each second amplifier in a center of the respective proximity group.
Claim 7
Dependent Claim
29 words
A method according to claim 1, further comprising the step of eliminating first conductive lines not connected to at least one second amplifier before determining the equivalent electrical diagram.
Claim 8
Dependent Claim
22 words
A method according to claim 6, further comprising the step of eliminating first amplifiers connected to the first conductive lines being eliminated.
Claim 9
Dependent Claim
34 words
A method according to claim 1, further comprising the step of eliminating portions of the second conductive lines located between two first conductive lines when there is no second amplifier connected to these portions.
Claim 10
Dependent Claim
42 words
A method according to claim 1, wherein the step of positioning the plurality of first conductive lines comprises placing the plurality of first conductive lines on a layer of the integrated circuit corresponding to a layer used to supply the clock signal.
Claim 11
Dependent Claim
31 words
A method according to claim 1, wherein the step of adjusting comprises adjusting as a function of a distance between each second amplifier and a closest edge of the integrated circuit.
Claim 12
Dependent Claim
39 words
A method according to claim 1, wherein the step of positioning the plurality of first and second conductive lines comprises positioning the plurality of first and second conductive lines on respective first and second layers of the integrated circuit.
Claim 13
Dependent Claim
37 words
A method according to claim 1, further comprising sizing each first amplifier as a function of a surface area of the plurality of first and second conductive lines connected to the output of a corresponding second amplifier.
Claim 14
Dependent Claim
51 words
A method according to claim 1, wherein each second amplifier comprises: an input stage comprising an input inverter receiving the clock signal, and at least one adjustment capacitor connected to an output of the input inverter producing a delay; and an output stage connected to the at least one adjustment capacitor.
Claim 15
Independent Claim
170 words
A method for positioning/routing a global clock circuit on an integrated circuit, the method comprising the steps of: positioning a plurality of first conductive lines on the integrated circuit in a first direction, each first conductive line being connected to at least one first amplifier having an input receiving a clock signal; positioning functional blocks forming the integrated circuit and positioning a plurality of second conductive lines on the integrated circuit parallel to a second direction, each second conductive line connected to a functional block; positioning in each functional block at least one second amplifier having an adjustable input delay, and routing one of the plurality of second conductive lines to each second amplifier; determining an equivalent electrical diagram corresponding to a clock signal path originating from a source and an input of each second amplifier; simulating the equivalent electrical diagram and measuring a phase delay at the input of each second amplifier; and adjusting the input delay of each second amplifier to correspond to a largest measured phase delay.
Claim 16
Independent Claim
170 words
A method for positioning/routing a global clock circuit on an integrated circuit, the method comprising the steps of: positioning a plurality of first conductive lines on the integrated circuit in a first direction, each first conductive line being connected to at least one first amplifier having an input receiving a clock signal; positioning functional blocks forming the integrated circuit and positioning a plurality of second conductive lines on the integrated circuit parallel to a second direction, each second conductive line connected to a functional block; positioning in each functional block at least one second amplifier having an adjustable input delay, and routing one of the plurality of second conductive lines to each second amplifier; determining an equivalent electrical diagram corresponding to a clock signal path originating from a source and an input of each second amplifier; simulating the equivalent electrical diagram and measuring a phase delay at the input of each second amplifier; and adjusting the input delay of each second amplifier to correspond to a largest measured phase delay.
Claim 17
Dependent Claim
28 words
A method according to claim 14, wherein the clock signal path originating from a single source forms a balanced tree-like structure with the at least one first amplifier.
Claim 18
Dependent Claim
75 words
A method according to claim 14, further comprising the steps of: positioning a plurality of devices in each functional block for receiving the clock signal; arranging the plurality of devices by proximity groups, each proximity group having at least one device less than or equal to a maximum number and being positioned over a surface area less than or equal to a maximum surface area; and positioning each second amplifier within a respective proximity group.
Claim 19
Dependent Claim
26 words
A method according to claim 16, further comprising the step of balancing the proximity groups with respect to a surface area of a corresponding functional block.
Claim 20
Dependent Claim
39 words
A method according to claim 16, wherein each second amplifier comprises an output transistor; the method further comprising the step of sizing each output transistor as a function of the at least one device within each corresponding proximity group.
Claim 21
Dependent Claim
27 words
A method according to claim 16, wherein the step of positioning each second amplifier comprises positioning each second amplifier in a center of the respective proximity group.
Claim 22
Dependent Claim
29 words
A method according to claim 16, further comprising the step of eliminating first conductive lines not connected to at least one second amplifier before determining the equivalent electrical diagram.
Claim 23
Dependent Claim
22 words
A method according to claim 14, further comprising the step of eliminating first amplifiers connected to the first conductive lines being eliminated.
Claim 24
Dependent Claim
34 words
A method according to claim 14, further comprising the step of eliminating portions of the second conductive lines located between two first conductive lines when there is no second amplifier connected to these portions.
Claim 25
Dependent Claim
42 words
A method according to claim 14, wherein the step of positioning the plurality of first conductive lines comprises placing the plurality of first conductive lines on a layer of the integrated circuit corresponding to a layer used to supply the clock signal.
Claim 26
Dependent Claim
31 words
A method according to claim 14, wherein the step of adjusting comprises adjusting as a function of a distance between each second amplifier and a closest edge of the integrated circuit.
Claim 27
Dependent Claim
39 words
A method according to claim 14, wherein the step of positioning the plurality of first and second conductive lines comprises positioning the plurality of first and second conductive lines on respective first and second layers of the integrated circuit.
Claim 28
Dependent Claim
37 words
A method according to claim 14, further comprising sizing each first amplifier as a function of a surface area of the plurality of first and second conductive lines connected to the output of a corresponding second amplifier.
Claim 29
Dependent Claim
51 words
A method according to claim 14, wherein each second amplifier comprises: an input stage comprising an input inverter receiving the clock signal, and at least one adjustment capacitor connected to an output of the input inverter producing a delay; and an output stage connected to the at least one adjustment capacitor.
Claim 30
Dependent Claim
169 words
An integrated circuit comprising: a plurality of functional blocks; a global clock circuit connected to said plurality of functional blocks providing a clock signal, said global clock circuit comprising a plurality of first amplifiers having an input receiving the clock signal, the clock signal originating from a source and forming a balanced tree-like structure with said plurality of first amplifiers, a plurality of first conductive lines parallel to a first direction, each first conductive line being connected to at least one of said plurality of first amplifiers, and a plurality of second conductive lines parallel to a second direction, each second conductive line being connected to at least one of said plurality of functional blocks; and each functional block comprising at least one second amplifier having an adjustable input delay connected to a closest one of said plurality of second conductive lines, the adjustable input delay being adjusted to correspond to a largest phase delay between the source clock signal and respective inputs of said plurality of second amplifiers.
Claim 31
Dependent Claim
169 words
An integrated circuit comprising: a plurality of functional blocks; a global clock circuit connected to said plurality of functional blocks providing a clock signal, said global clock circuit comprising a plurality of first amplifiers having an input receiving the clock signal, the clock signal originating from a source and forming a balanced tree-like structure with said plurality of first amplifiers, a plurality of first conductive lines parallel to a first direction, each first conductive line being connected to at least one of said plurality of first amplifiers, and a plurality of second conductive lines parallel to a second direction, each second conductive line being connected to at least one of said plurality of functional blocks; and each functional block comprising at least one second amplifier having an adjustable input delay connected to a closest one of said plurality of second conductive lines, the adjustable input delay being adjusted to correspond to a largest phase delay between the source clock signal and respective inputs of said plurality of second amplifiers.
Claim 32
Dependent Claim
25 words
An integrated circuit according to claim 28, wherein each one of said plurality of functional blocks comprises a plurality of devices receiving the clock signal.
Claim 33
Dependent Claim
51 words
An integrated circuit according to claim 29, wherein said plurality of devices are arranged by proximity groups, and wherein each proximity group has at least one device less than or equal to a maximum number and is positioned over a surface area less than or equal to a maximum surface area.
Claim 34
Dependent Claim
18 words
An integrated circuit according to claim 30, wherein each second amplifier is positioned within a respective proximity group.
Claim 35
Dependent Claim
24 words
An integrated circuit according to claim 31, wherein said proximity groups are balanced with respect to a surface area of a corresponding functional block.
Claim 36
Dependent Claim
27 words
An integrated circuit according to claim 28, wherein said plurality of first conductive lines are on a first layer corresponding to a layer providing the clock signal.
Claim 37
Dependent Claim
23 words
An integrated circuit according to claim 28, wherein said plurality of first and second conductive lines are on respective first and second layers.
Claim 38
Dependent Claim
57 words
An integrated circuit according to claim 28, wherein each one of said plurality of second amplifiers comprises: an input stage comprising an input inverter receiving the clock signal, and at least one adjustment capacitor connected to an output of said input inverter producing a delay; and an output stage connected to said at least one adjustment capacitor.
References Cited (Backward Citations)
US5744856A
Cited
US5994777A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-21 | 2004-05-22 | 2004-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-21 | 2008-05-22 | 2008-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-21 | 2012-05-22 | 2012-11-21 | $7700.00 | Window Closed / Lapsed |