Patent US6313819B1 successfully refreshed from Google Patents.
Patent US6939727B1 successfully refreshed from Google Patents.
US6939727B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for performing statistical post processing in semiconductor manufacturing using ID cells
Assignee: Bell Semiconductor LLC
•
Filing: 2003-11-03
•
Granted: 2005-09-06
•
Expires: 2023-11-03
Abstract
Abstract A method of manufacturing a semiconductor integrated circuit includes providing a fabricated integrated circuit on a wafer. A test fixture is connected to unencapsulated pads on the integrated circuit to monitor an operating parameter for the circuit and to determine a unique identifier for the die. The parameter is analyzed in post processing.
Inventors
- 👤 Ernest Allen, III
- 👤 David Castaneda
- 👤 Miaw Looi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:50
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; H10P74/27; H10P74/277; H10W; H10W46/00; H10W46/601; H10W46/603
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
86 words
A method for manufacturing a semiconductor integrated circuit, the method comprising: providing a wafer having a plurality of integrated circuit dies; using a test fixture to provide electrical contact with electrical testing structures located in a scribe line adjacent to a first of the plurality of integrated circuit dies; and monitoring the output of an identification cell located within the first of the plurality of integrated circuit dies by using the test fixture to provide contact with contacts on the wafer corresponding to the identification cell.
Claim 2
Independent Claim
86 words
A method for manufacturing a semiconductor integrated circuit, the method comprising: providing a wafer having a plurality of integrated circuit dies; using a test fixture to provide electrical contact with electrical testing structures located in a scribe line adjacent to a first of the plurality of integrated circuit dies; and monitoring the output of an identification cell located within the first of the plurality of integrated circuit dies by using the test fixture to provide contact with contacts on the wafer corresponding to the identification cell.
Claim 3
Dependent Claim
36 words
The method as recited in claim 1 wherein the contacts are electrically connected to the identification cell and positioned in a predetermined standardized geometric location relative to the electrical testing structures located in the scribe line.
Claim 4
Dependent Claim
13 words
The method as recited in claim 1 wherein the contacts are metallic pads.
Claim 5
Dependent Claim
33 words
The method as recited in claim 1 further comprising using the test fixture to access a contact on at least one of the plurality of integrated circuit dies to measure a performance parameter.
Claim 6
Dependent Claim
21 words
The method as recited in claim 4 wherein the performance parameter is one of a supply current and a supply voltage.
Claim 7
Dependent Claim
15 words
The method as recited in claim 4 wherein the performance parameter is a quiescent current.
Claim 8
Dependent Claim
50 words
The method as recited in claim 1 , wherein the output of an identification cell provides a unique identification number for the cell and further comprising storing the identification number along with location data indicating the location of the first of the plurality of integrated circuit dies on the wafer.
Claim 9
Dependent Claim
30 words
The method as recited in claim 7 further comprising using the identification number and the location data in a post processing step to identify defects in the plurality of dies.
Claim 10
Dependent Claim
86 words
An integrated circuit test fixture configured for interconnection between a semiconductor tester and a wafer, comprising: a plurality of probe tips configured to provide electrical contact with a corresponding plurality of pads on a semiconductor wafer, wherein a first group of the plurality of pads comprises pads connected to an identification cell located within an integrated circuit die on the wafer and a second group of the plurality of pads is connected to an electrical testing structure located in a scribe line adjacent to the die.
Claim 11
Dependent Claim
86 words
An integrated circuit test fixture configured for interconnection between a semiconductor tester and a wafer, comprising: a plurality of probe tips configured to provide electrical contact with a corresponding plurality of pads on a semiconductor wafer, wherein a first group of the plurality of pads comprises pads connected to an identification cell located within an integrated circuit die on the wafer and a second group of the plurality of pads is connected to an electrical testing structure located in a scribe line adjacent to the die.
Claim 12
Dependent Claim
42 words
The integrated circuit test fixture as recited in claim 9 wherein the plurality of pads are located in a corner of the integrated circuit die adjacent to the location of electrical testing structure located in a scribe line adjacent to the die.
Claim 13
Dependent Claim
43 words
The integrated circuit test fixture as recited in claim 9 wherein a third group of the plurality of pads is connected to a reference test cell located on the integrated circuit die and configured to measure an electrical parameter for the integrated circuit.
Claim 14
Dependent Claim
18 words
The integrated circuit test fixture as recited in claim 11 wherein the electrical parameter is a supply current.
Claim 15
Dependent Claim
38 words
The integrated circuit test fixture as recited in clam 9 wherein the plurality of probe tips are connected to a printed circuit board of the test fixture, the printed circuit board configured for electrical connection to a tester.
Claim 16
Dependent Claim
38 words
The integrated circuit test fixture as recited in clam 9 wherein the plurality of probe tips are connected to a printed circuit board of the test fixture, the printed circuit board configured for electrical connection to a tester.
Claim 17
Independent Claim
86 words
A method of manufacturing a semiconductor integrated circuit, the method comprising: providing a wafer having a plurality of dies; generating an identification number from an identification cell located on each of the plurality of dies; monitoring the identification number before separating the plurality of dies from the wafer by using a generic interface configured to access pads on a plurality of different integrated circuit designs; and using the monitored identification number in a statistical post processing to identify defects in any of the plurality of dies.
Claim 18
Independent Claim
86 words
A method of manufacturing a semiconductor integrated circuit, the method comprising: providing a wafer having a plurality of dies; generating an identification number from an identification cell located on each of the plurality of dies; monitoring the identification number before separating the plurality of dies from the wafer by using a generic interface configured to access pads on a plurality of different integrated circuit designs; and using the monitored identification number in a statistical post processing to identify defects in any of the plurality of dies.
Claim 19
Dependent Claim
16 words
The method recited in claim 14 , wherein the statistical post processing identifies wafer defect patterns.
Claim 20
Dependent Claim
46 words
The method recited in claim 15 , further comprising correlating the monitoring identification number with a physical location of the die on the wafer and wherein the wafer defect patterns are determined using the identification number and the physical location of the die on the wafer.
Claim 21
Dependent Claim
24 words
The method recited in claim 15 , wherein the generic interface is configured to conform to a standardized configuration of pads on the wafers.
Claim 22
Dependent Claim
29 words
The method recited in claim 15 , wherein the test interface is configured to access e-test structure pads at the same time that the identification cell signals are monitored.
Claim 23
Dependent Claim
26 words
The method recited in claim 18 , further comprising monitoring a signal from a reference test cell within at least one of the plurality of dies.
Claim 24
Dependent Claim
21 words
The method recited in claim 14 wherein the post processing occurs after the plurality of dies are separated from the wafer.
Claim 25
Independent Claim
115 words
A method for manufacturing a semiconductor integrated circuit, the method comprising: providing a wafer having a plurality of integrated circuit dies; using a test fixture to provide electrical contact with electrical testing structures located in a scribe line adjacent to a first of the plurality of integrated circuit dies; and monitoring the output of an identification cell located within the first of the plurality of integrated circuit dies by using the test fire to provide contact with contacts on the wafer corresponding to the identification cell wherein the contacts are electrically connected to the identification cell and positioned in a predetermined standardized geometric location relative to the electrical testing structures located in the scribe line.
Claim 26
Independent Claim
115 words
A method for manufacturing a semiconductor integrated circuit, the method comprising: providing a wafer having a plurality of integrated circuit dies; using a test fixture to provide electrical contact with electrical testing structures located in a scribe line adjacent to a first of the plurality of integrated circuit dies; and monitoring the output of an identification cell located within the first of the plurality of integrated circuit dies by using the test fire to provide contact with contacts on the wafer corresponding to the identification cell wherein the contacts are electrically connected to the identification cell and positioned in a predetermined standardized geometric location relative to the electrical testing structures located in the scribe line.
Claim 27
Independent Claim
128 words
A method for manufacturing a semiconductor integrated circuit, the method comprising: providing a wafer having a plurality of integrated circuit dies; using a test fixture to provide electrical contact with electrical testing structures located in a scribe line adjacent to a first of the plurality of integrated circuit dies; monitoring the output of an identification cell located within the first of the plurality of integrated circuit dies by using the test fixture to provide contact with contacts on the wafer corresponding to the identification cell; and using the test fixture to access a contact on at least one of the plurality of integrated circuit dies to measure a performance parameter wherein the performance parameter at least one of a supply current, a supply voltage, and a quiescent current.
Claim 28
Independent Claim
128 words
A method for manufacturing a semiconductor integrated circuit, the method comprising: providing a wafer having a plurality of integrated circuit dies; using a test fixture to provide electrical contact with electrical testing structures located in a scribe line adjacent to a first of the plurality of integrated circuit dies; monitoring the output of an identification cell located within the first of the plurality of integrated circuit dies by using the test fixture to provide contact with contacts on the wafer corresponding to the identification cell; and using the test fixture to access a contact on at least one of the plurality of integrated circuit dies to measure a performance parameter wherein the performance parameter at least one of a supply current, a supply voltage, and a quiescent current.
Claim 29
Independent Claim
119 words
A method for manufacturing a semiconductor integrated circuit, the method comprising: providing a wafer having a plurality of integrated circuit dies; using a test fixture to provide electrical contact with electrical testing structures located in a scribe line adjacent to a first of the plurality of integrated circuit dies; monitoring the output of an identification cell located within the first of the plurality of integrated circuit dies by using the test fixture to provide contact with contacts on the wafer corresponding to the identification cell thereby providing a unique identification number for the cell; and storing the identification number along with location data indicating the location of the first of the plurality of integrated circuit dies on the wafer.
Claim 30
Independent Claim
119 words
A method for manufacturing a semiconductor integrated circuit, the method comprising: providing a wafer having a plurality of integrated circuit dies; using a test fixture to provide electrical contact with electrical testing structures located in a scribe line adjacent to a first of the plurality of integrated circuit dies; monitoring the output of an identification cell located within the first of the plurality of integrated circuit dies by using the test fixture to provide contact with contacts on the wafer corresponding to the identification cell thereby providing a unique identification number for the cell; and storing the identification number along with location data indicating the location of the first of the plurality of integrated circuit dies on the wafer.
Claim 31
Dependent Claim
30 words
The method as recited in claim 23 further comprising using the identification number and the location data in a post processing step to identify defects in the plurality of dies.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-09-05 | 2009-03-07 | 2009-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-09-05 | 2013-03-07 | 2013-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-09-05 | 2017-03-07 | 2017-09-06 | $7700.00 | Window Closed / Lapsed |