US6714031B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device for wafer examination
Assignee: Seiko Epson Corp
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Filing: 2002-05-21
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Granted: 2004-03-30
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Expires: 2022-05-21
Abstract
Abstract The invention provides a semiconductor device that enables examination of a wafer in an initial stage to check whether the wafer is acceptable or defective in the case of DC examinations for circuit elements and also AC examinations for circuit delay times and the like. A semiconductor device is equipped with (a) a semiconductor wafer including a plurality of chip regions in which a required circuit is formed, and a scribe region to divide the plurality of chip regions, (b) a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors, and (c) an output pad formed in the scribe region and connected to the test circuit.
Inventors
- 👤 Hiroshi Seki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:38
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/277
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
89 words
A semiconductor device, comprising: a semiconductor wafer including a plurality of chip regions in which a specified circuit is formed, and a scribe region to divide the plurality of chip regions; a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors; an output pad formed in the scribe region and connected to the test circuit; and an input pad formed in the scribe region and connected to the test circuit, the test circuit including a plurality of serially connected inversion circuits.
Claim 2
Dependent Claim
89 words
A semiconductor device, comprising: a semiconductor wafer including a plurality of chip regions in which a specified circuit is formed, and a scribe region to divide the plurality of chip regions; a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors; an output pad formed in the scribe region and connected to the test circuit; and an input pad formed in the scribe region and connected to the test circuit, the test circuit including a plurality of serially connected inversion circuits.
Claim 3
Dependent Claim
29 words
The semiconductor device according to claim 1 , the plurality of transistors formed in the scribe region for wafer examination being uniformly configured with respect to the specified circuit.
Claim 4
Dependent Claim
35 words
The semiconductor device according to claim 1 , the plurality of transistors formed in the scribe region for wafer examination forming a cell having a configuration of a basic cell formed in the chip regions.
Claim 5
Dependent Claim
183 words
A semiconductor device, comprising: a semiconductor wafer including a plurality of chip regions in which a specified circuit is formed, and a scribe region to divide the plurality of chip regions; a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors: an output pad formed in the scribe region and connected to the test circuit; and an input pad formed in the scribe reagon and connected to the test circuit, the test circuit including a selector circuit that supplies a signal supplied from the input pad to at least one of a first output and a second output according to a control signal, a plurality of inverter circuits serially connected to a first output of the selector circuit, and an output circuit that supplies to the output pad one of an output signal of the last stage of the plurality of inverter circuits and a second output signal of the selector circuit, and the semiconductor device further including a control pad formed in the scribe region to input a control signal to the selector circuit.
Claim 6
Dependent Claim
183 words
A semiconductor device, comprising: a semiconductor wafer including a plurality of chip regions in which a specified circuit is formed, and a scribe region to divide the plurality of chip regions; a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors: an output pad formed in the scribe region and connected to the test circuit; and an input pad formed in the scribe reagon and connected to the test circuit, the test circuit including a selector circuit that supplies a signal supplied from the input pad to at least one of a first output and a second output according to a control signal, a plurality of inverter circuits serially connected to a first output of the selector circuit, and an output circuit that supplies to the output pad one of an output signal of the last stage of the plurality of inverter circuits and a second output signal of the selector circuit, and the semiconductor device further including a control pad formed in the scribe region to input a control signal to the selector circuit.
Claim 7
Dependent Claim
140 words
A semiconductor device, comprising: a semiconductor wafer including a plurality of chip regions in which a specified circuit is formed, and a scribe region to divide the plurality of chip regions: a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors; an output pad formed in the scribe region and connected to the test circuit; and an input pad formed in the scribe region and connected to the test circuit, the test circuit including a plurality of inverter circuits serially connected to the input pad, and an output circuit that produces an exclusive OR of an output signal of the last stage of the plurality of inverter circuits and an input signal supplied to the input pad and supplies one of the output signal and the input signal to the output pad.
Claim 8
Dependent Claim
140 words
A semiconductor device, comprising: a semiconductor wafer including a plurality of chip regions in which a specified circuit is formed, and a scribe region to divide the plurality of chip regions: a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors; an output pad formed in the scribe region and connected to the test circuit; and an input pad formed in the scribe region and connected to the test circuit, the test circuit including a plurality of inverter circuits serially connected to the input pad, and an output circuit that produces an exclusive OR of an output signal of the last stage of the plurality of inverter circuits and an input signal supplied to the input pad and supplies one of the output signal and the input signal to the output pad.
Claim 9
Dependent Claim
107 words
A semiconductor device, comprising: a semiconductor wafer including a plurality of chip regions in which a specified circuit is formed, and a scribe region to divide the plurality of chip regions; a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors; an output pad formed in the scribe region and connected to the test circuit, the test circuit including a plurality of circuits that are connected in a loop, invert an input signal and output the inverted input signal, and an output circuit that supplies an output signal of one of the plurality of circuits to the output pad.
Claim 10
Dependent Claim
107 words
A semiconductor device, comprising: a semiconductor wafer including a plurality of chip regions in which a specified circuit is formed, and a scribe region to divide the plurality of chip regions; a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors; an output pad formed in the scribe region and connected to the test circuit, the test circuit including a plurality of circuits that are connected in a loop, invert an input signal and output the inverted input signal, and an output circuit that supplies an output signal of one of the plurality of circuits to the output pad.
Claim 11
Dependent Claim
50 words
The semiconductor device according to claim 6 , the plurality of circuits including at least one NAND circuit, and the semiconductor device further including a control pad that is formed in the scribe region to supply a control signal to one of inputs of the at least one NAND circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-03-30 | 2007-09-29 | 2008-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-03-30 | 2011-09-29 | 2012-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-03-30 | 2015-09-29 | 2016-03-30 | $7700.00 | Window Closed / Lapsed |