US6400173B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test system and manufacturing of semiconductor device
Assignee: Hitachi Ltd
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Filing: 2000-10-20
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Granted: 2002-06-04
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Expires: 2020-10-20
Abstract
Abstract A test circuit is provided on a probe card or a wafer on which semiconductor chips to be tested are formed. The test circuit and each of the semiconductor chips to be tested are electrically connected to each other to perform testing, whereby the test can be carried out without using a tester. Conducting a test in such a wafer stage within an aging device allows the simplification or omission of a test subsequent to packaging.
Inventors
- 👤 Isao Shimizu
- 👤 Masayuki Sato
- 👤 Hiroshi Fukiage
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:04
CPC Classifications
H; H10; H10P; H10P74/00; H10P72/00; H10P72/70; H10P72/74; G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/2801; G01R31/2806; G01R31/282; G01R31/2831; G01R31/2886; H10W; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
107 words
A test system which performs electrical tests on semiconductor chips formed on a semiconductor wafer, comprising: a probe card which is provided with conductive needles in alignment with the placement of electrode pads in the semiconductor chips and connected to a plurality of test circuits, each of said test circuits being placed on said probe card, and arranged to provide test input signals to said semiconductor chips and receive output signals from said semiconductor chips to generate a test result based on a program; and a control device which writes said program in said test circuit and stores therein said test result outputted from said test circuit.
Claim 2
Dependent Claim
107 words
A test system which performs electrical tests on semiconductor chips formed on a semiconductor wafer, comprising: a probe card which is provided with conductive needles in alignment with the placement of electrode pads in the semiconductor chips and connected to a plurality of test circuits, each of said test circuits being placed on said probe card, and arranged to provide test input signals to said semiconductor chips and receive output signals from said semiconductor chips to generate a test result based on a program; and a control device which writes said program in said test circuit and stores therein said test result outputted from said test circuit.
Claim 3
Dependent Claim
19 words
The test system according to claim 1 , wherein said test circuit includes an FPGA or a microcomputer device.
Claim 4
Dependent Claim
20 words
A test system according to claim 1 , wherein the test circuits are test chips mounted on the probe card.
Claim 5
Dependent Claim
28 words
A test system according to claim 1 , wherein the probe card comprises a frame and a semiconductor substrate in which the plurality of test circuits are formed.
Claim 6
Dependent Claim
21 words
A test system according to claim 4 , wherein the conductive needles are formed on a surface of the semiconductor substrate.
Claim 7
Dependent Claim
84 words
A test system which conducts electrical tests on semiconductor chips formed on a semiconductor wafer, comprising: a test circuit, which provides test input signals to said semiconductor chips and receives output signals from said semiconductor chips to generate a test result, formed on said semiconductor wafer, a probing module having test wirings formed therein, which connect the semiconductor chips and said test circuit; and a power supply device which supplies power to said each semiconductor chip and said test circuit through said probing module.
Claim 8
Dependent Claim
84 words
A test system which conducts electrical tests on semiconductor chips formed on a semiconductor wafer, comprising: a test circuit, which provides test input signals to said semiconductor chips and receives output signals from said semiconductor chips to generate a test result, formed on said semiconductor wafer, a probing module having test wirings formed therein, which connect the semiconductor chips and said test circuit; and a power supply device which supplies power to said each semiconductor chip and said test circuit through said probing module.
Claim 9
Dependent Claim
19 words
The test system according to claim 6 , wherein said test circuit includes an FPGA or a microcomputer device.
Claim 10
Dependent Claim
25 words
The test system according to claim 7 , wherein said test circuit conducts tests on a plurality of semiconductor chips formed on a semiconductor wafer.
Claim 11
Dependent Claim
24 words
A test system according to claim 6 , wherein the test circuit is surrounded by a plurality of said semiconductor chips to be tested.
Claim 12
Dependent Claim
88 words
A test system which performs electrical tests on semiconductor chips formed on a semiconductor wafer, comprising: a test circuit which provides test input signals to said semiconductor chips and receives output signals from said semiconductor chips to generate a test a result, wherein said test circuit is formed in a scribe area or a chip area in the semiconductor wafer; and test wirings which are formed in the scribe area or a test wiring layer in the semiconductor wafer and connect said test circuit to the semiconductor chips.
Claim 13
Dependent Claim
88 words
A test system which performs electrical tests on semiconductor chips formed on a semiconductor wafer, comprising: a test circuit which provides test input signals to said semiconductor chips and receives output signals from said semiconductor chips to generate a test a result, wherein said test circuit is formed in a scribe area or a chip area in the semiconductor wafer; and test wirings which are formed in the scribe area or a test wiring layer in the semiconductor wafer and connect said test circuit to the semiconductor chips.
Claim 14
Dependent Claim
19 words
The test system according to claim 10 , wherein said test circuit includes an FPGA or a microcomputer device.
Claim 15
Dependent Claim
25 words
The test system according to claim 11 , wherein said test circuit conducts tests on a plurality of semiconductor chips formed on a semiconductor wafer.
References Cited (Backward Citations)
US6246245B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-06-03 | 2005-12-03 | 2006-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-06-03 | 2009-12-03 | 2010-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-06-03 | 2013-12-03 | 2014-06-04 | $7700.00 | Window Closed / Lapsed |