Patent US6904110B2 successfully refreshed from Google Patents.
US6904110B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Channel equalization system and method
Assignee: BC LEOW
•
Filing: 2001-05-01
•
Granted: 2005-06-07
•
Expires: 2021-05-01
Abstract
Abstract A system and method for delivering increases speed, security, and intelligence to wireline and wireless systems. The present invention increases channel capacity by using a parallel or multi-channel structure in such wireless and wireline at the edge or the core of. This new architecture of the present invention uses parallel bitstreams in a flexible way and distributed switching/routing technique, is not only to avoid the potential bottlenet of centralized switches, but also to increase speed with intelligence that is seamlessly integrating into the Fiber Optic Backbone such as WDM and SONET of the MAN/WAN network with a Real-time guarantees, different types of traffic (such as Stringent synchronous, isochronous, and asynchronous data messages) with different demands, and privacy & security of multi access and integrated services environment.
Inventors
- 👤 Francois Trans
- 👤 Tho Le-Ngoc
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:03
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/20; H04L1/205; H04B; H04B1/00; H04B3/00; H04B3/02; H04B3/32; H04L1/0001; H04L1/0002; H04L1/004; H04L1/0045; H04L1/0054; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03019; H04L25/03038; H04L25/08; H04L25/085; H04L25/14; H04L25/38; H04L25/40; H04L25/49; H04L25/497; H04L5/00; H04L5/14; H04L5/143; H04L5/16; H04L7/00; H04L7/0008; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0638; H04L2025/0335; H04L2025/03356; H04L2025/03363; H04L2025/03433; H04L2025/03439; H04L2025/03445; H04L2025/03471; H04L2025/03484; H04L2025/0349; H04L2025/03509; H04L5/0001; H04L5/0003; H04L5/0005; H04L5/0007
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
284 words
A system for reducing interference in a communication system, the interference occurring on a data sample signal having a precursor inter-symbol interference (ISI) portion and a post-cursor ISI portion, the system comprising: a first precursor equalizer, for receiving the data sample signal and for performing an equalization operation on said data sample signal to reduce the precursor ISI and to generate an ISI equalized sample signal; a summer, coupled to said first precursor equalizer, for combining said ISI equalized sample signal and a post-cursor cancellation signal to generate an equalized estimated sample signal; a slicer, coupled to said summer to receive said equalized estimated sample signal, for generating a detected symbol signal representing a preliminary symbol value of said equalized estimated sample signal; a precursor canceller, for receiving said equalized estimated sample signal and said detected symbol signal, for further reducing the precursor interference, said precursor canceller having: a finite impulse response filter, for receiving said detected symbol signal and for determining the precursor ISI on said detected symbol signal to generate a precursor cancellation signal, a first delay component to receive said equalized estimated sample signal, for delaying said equalized estimated sample signal by a first amount and to output a delayed equalized estimated sample signal, said first amount corresponding to a delay caused by said slicer and finite impulse response filter, a DPIC summer to combine said precursor cancellation signal and said delayed equalized estimated sample signal to generate a second output signal representing said data sample signal having a reduced precursor interference portion; and a first post-cursor canceller, for receiving said detected symbol signal, and for reducing the post-cursor interference on said detected symbol signal to generate said post-cursor cancellation signal.
Claim 2
Independent Claim
284 words
A system for reducing interference in a communication system, the interference occurring on a data sample signal having a precursor inter-symbol interference (ISI) portion and a post-cursor ISI portion, the system comprising: a first precursor equalizer, for receiving the data sample signal and for performing an equalization operation on said data sample signal to reduce the precursor ISI and to generate an ISI equalized sample signal; a summer, coupled to said first precursor equalizer, for combining said ISI equalized sample signal and a post-cursor cancellation signal to generate an equalized estimated sample signal; a slicer, coupled to said summer to receive said equalized estimated sample signal, for generating a detected symbol signal representing a preliminary symbol value of said equalized estimated sample signal; a precursor canceller, for receiving said equalized estimated sample signal and said detected symbol signal, for further reducing the precursor interference, said precursor canceller having: a finite impulse response filter, for receiving said detected symbol signal and for determining the precursor ISI on said detected symbol signal to generate a precursor cancellation signal, a first delay component to receive said equalized estimated sample signal, for delaying said equalized estimated sample signal by a first amount and to output a delayed equalized estimated sample signal, said first amount corresponding to a delay caused by said slicer and finite impulse response filter, a DPIC summer to combine said precursor cancellation signal and said delayed equalized estimated sample signal to generate a second output signal representing said data sample signal having a reduced precursor interference portion; and a first post-cursor canceller, for receiving said detected symbol signal, and for reducing the post-cursor interference on said detected symbol signal to generate said post-cursor cancellation signal.
Claim 3
Dependent Claim
18 words
The system of claim 1 , wherein said post-cursor canceller includes a plurality of taps having input coefficients.
Claim 4
Dependent Claim
22 words
The system of claim 2 , wherein said coefficients automatically adjust in response to the post-cursor interference on the data sample signal.
Claim 5
Dependent Claim
24 words
The system of claim 1 , wherein said first precursor equalizer includes a plurality of taps having input coefficients to reduce the pre-cursor interference.
Claim 6
Dependent Claim
24 words
The system of claim 1 , wherein said finite response filter includes a plurality of taps having input coefficients to reduce the pre-cursor interference.
Claim 7
Dependent Claim
22 words
The system of claim 1 , wherein said first delay component aligns said equalized estimated sample signal and said slicer output signal.
Claim 8
Dependent Claim
100 words
The system of claim 1 , further comprising: a second delay component, coupled to receive said data sample signal, for delaying said data sample signal by a second amount and for outputting a delayed data sample signal; and a second precursor equalizer, for receiving said delayed data sample signal and for performing an equalization operation on said delayed data sample signal to reduce precursor interference and to generate a delayed equalized signal; wherein said DPIC summer receives said delayed precursor equalized output wherein said delayed equalized estimated sample signal represents said data sample signal having a reduced precursor interference portion.
Claim 9
Dependent Claim
37 words
The system of claim 7 , wherein said second amount corresponds to a delay caused by said first precursor equalizer, said summer, and said first delay component reduced by the delay caused by said second precursor equalizer.
Claim 10
Dependent Claim
24 words
The system of claim 7 , wherein said second precursor equalizer includes a plurality of taps having input coefficients to reduce the pre-cursor interference.
Claim 11
Dependent Claim
100 words
The system of claim 7 , further comprising: a DPIC slicer, coupled to said DPIC summer to receive said second output signal, for generating a DPIC slicer output signal representing a preliminary value of said second output signal; and a second post-cursor canceller, for receiving said DPIC slicer output signal, and for reducing the post-cursor interference of said DPIC slicer output signal to generate a DPIC post-cursor cancellation signal; wherein said DPIC summer combines said DPIC post-cursor cancellation signal with said precursor cancellation signal, said delayed equalized estimated sample signal and said delayed equalized signal to generate said second output.
Claim 12
Dependent Claim
19 words
The system of claim 10 , wherein said second post-cursor canceller includes a plurality of taps having input coefficients.
Claim 13
Dependent Claim
22 words
The system of claim 11 , wherein said coefficients automatically adjust in response to the post-cursor interference on the data sample signal.
References Cited (Backward Citations)
US4412341A
Cited
US4630217A
Cited
US4648060A
Cited
US4905282A
Cited
US5111208A
Cited
US5181228A
Cited
US5162723A
Cited
US5293402A
Cited
US5541955A
Cited
US5550810A
Cited
US5841667A
Cited
US5625651A
Cited
US5754352A
Cited
US5812594A
Cited
US5675612A
Cited
US5680451A
Cited
US5930267A
Cited
US5787363A
Cited
US6538986B2
Cited
US5864545A
Cited
US6377640B2
Cited
US6553085B1
Cited
US6144697A
Cited
US6236645B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-06-06 | 2008-12-06 | 2009-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-06-06 | 2012-12-06 | 2013-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-06-06 | 2016-12-06 | 2017-06-07 | $7700.00 | Window Closed / Lapsed |