US5754352A
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US
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Synchronous read channel employing an expected sample value generator for acquiring a preamble
Assignee: Cirrus Logic Inc
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Filing: 1996-08-22
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Granted: 1998-05-19
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Expires: 2016-08-22
Abstract
Abstract An improved timing recovery phase-locked loop in a partial response recording channel comprising a means for generating a frequency error and a means for generating a phase error represented by a timing gradient. The frequency error is not affected by a DC offset in the input reference signal and is less susciptible to noise due to an increase in sensitivity. A state machine for generating expected samples is used to generate the timing gradient, rather than estimated signal samples, which results in a shorter acquisition preamble. When tracking arbitrary user data, the timing gradient is smoothed to reduce variations in the gain of the loop.
Inventors
- 👤 Richard T. Behrens
- 👤 Trent Dudley
- 👤 William G. Bliss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:03
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; H; H04; H04L; H04L7/00; H04L7/0054; H04L7/0062; G11B20/10009; G11B20/10046; G11B20/10055; G11B20/14; G11B20/1403; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/091; H04L7/02; H04L7/033; H04L7/0334; H04L7/04; H04L7/10
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
168 words
A timing recovery circuit in a synchronous read channel utilized in reading data from a magnetic medium, said synchronous read channel detects digital data from a sequence of discrete time sample values Y(n) generated by sampling pulses in an analog signal from a magnetic read head positioned over the magnetic medium, said timing recovery circuit for adjusting the phase and frequency of a sampling clock signal relative to the phase and frequency of the pulse data, said timing recovery circuit comprises a phase detector circuit comprising: (a) a timing gradient circuit for generating a timing gradient value .increment.t(n) representing a minimum mean squared error between the discrete time sample values Y(n) and a corresponding a priori sequence of expected sample values X(n) corresponding to sample values of a known acquisition preamble; and (b) an expected sample value generator for generating the a prior sequence of expected sample values X(n), wherein at least one of the expected sample values X(n) is generated independent from the discrete time sample values.
Claim 2
Dependent Claim
168 words
A timing recovery circuit in a synchronous read channel utilized in reading data from a magnetic medium, said synchronous read channel detects digital data from a sequence of discrete time sample values Y(n) generated by sampling pulses in an analog signal from a magnetic read head positioned over the magnetic medium, said timing recovery circuit for adjusting the phase and frequency of a sampling clock signal relative to the phase and frequency of the pulse data, said timing recovery circuit comprises a phase detector circuit comprising: (a) a timing gradient circuit for generating a timing gradient value .increment.t(n) representing a minimum mean squared error between the discrete time sample values Y(n) and a corresponding a priori sequence of expected sample values X(n) corresponding to sample values of a known acquisition preamble; and (b) an expected sample value generator for generating the a prior sequence of expected sample values X(n), wherein at least one of the expected sample values X(n) is generated independent from the discrete time sample values.
Claim 3
Dependent Claim
20 words
The timing recovery circuit as recited in claim 1, wherein the timing gradient value .increment.t(n) is computed as: .increment.t(n)=Y(n-1)·X(n)-Y(n)·X(n-1). 3.
Claim 4
Dependent Claim
35 words
The timing recovery circuit as recited in claim 1, wherein the expected sample value generator is initialized to a starting state in response to the sign of two of the discrete time sample values Y(n).
Claim 5
Dependent Claim
38 words
The timing recovery circuit as recited in claim 1, wherein the expected sample value generator is initialized to a starting state in response to the sign and absolute magnitude of two of the discrete time sample values Y(n).
Claim 6
Dependent Claim
95 words
The timing recovery circuit as recited in claim 1, wherein the expected sample value generator comprises a discrete time counter comprising: (a) a clock input connected to the sampling clock; and (b) a discrete time output for outputting the counter value, representing the expected sample value, at the sampling clock rate, wherein the counter is loaded with a starting state value in response to a predetermined number of the discrete time sample values Y(n) and thereafter generates the expected sample values X(n) by sequencing through a plurality of predetermined states at each sample clock period.
Claim 7
Dependent Claim
96 words
The timing recovery circuit as recited in claim 1, wherein the timing recovery circuit is utilized in acquiring a known preamble of pulses in a substantially periodic form, wherein: (a) the expected sample values of the preamble are of the form +A,+A,-A,-A,+A,+A,-A,-A . . . ; and (b) the +A,+A values of the preamble correspond to a first pair of discrete values on each side, respectively, of the positive pulse peaks; and (c) the -A,-A values of the preamble correspond to a second pair of discrete values on each side, respectively, of the negative pulse peaks.
Claim 8
Dependent Claim
113 words
The timing recovery circuit as recited in claim 1, wherein the timing recovery circuit is utilized in acquiring a known preamble of pulses in a substantially periodic form, wherein: (a) the expected sample values of the preamble are of the form +A,0,-A,0,+A,0,-A,0. . . ; and (b) the +A values of the preamble correspond to a first discrete value at the peak of the positive pulses; and (c) the -A values of the preamble correspond to a second discrete value at the peak of the negative pulses; and (d) the 0 values of the preamble correspond to a third discrete time value at the beginning and ending of the positive and negative pulses.
Claim 9
Dependent Claim
125 words
The timing recovery circuit as recited in claim 1, further comprising: (a) a circuit for generating a sequence of estimated sample values ˜X(n) in response to the discrete time sample values Y(n); and (b) a multiplexer for transmitting to the timing gradient circuit the expected sample values X(n) during acquisition of a predetermined preamble, and the estimated sample values ˜X(n) during tracking of arbitrary data; and wherein the timing gradient circuit generates the timing gradient value .increment.t(n) as: a minimum mean squared error between the discrete time sample values Y(n) and the corresponding sequence of expected sample values X(n) during acquisition; and a minimum mean squared error between the discrete time sample values Y(n) and the corresponding sequence of estimated sample values ˜X(n) during tracking.
Claim 10
Dependent Claim
42 words
The timing recovery circuit as recited in claim 1, further comprising a variable frequency oscillator having said sampling clock signal as an output, wherein the variable frequency oscillator adjusts the frequency of the sampling clock in response to the timing gradient .increment.t(n).
Claim 11
Dependent Claim
158 words
A timing recovery method in a synchronous read channel utilized in reading data from a magnetic medium, said synchronous read channel detects digital data from a sequence of discrete time sample values Y(n) generated by sampling pulses in an analog signal from a magnetic read head positioned over the magnetic medium, said timing recovery method for adjusting the phase and frequency of a sampling clock signal relative to the phase and frequency of the pulse data, said timing recovery method comprising the steps of: (b) generating an a priori sequence of expected sample values X(n) corresponding to the discrete time sample values of a known acquisition preamble, wherein at least one of the expected sample values X(n) is generated independent from the discrete time sample values; and (a) generating a timing gradient value .increment.t(n) representing a minimum mean squared error between the discrete time sample values Y(n) and the corresponding a priori sequence of expected sample values X(n).
Claim 12
Dependent Claim
158 words
A timing recovery method in a synchronous read channel utilized in reading data from a magnetic medium, said synchronous read channel detects digital data from a sequence of discrete time sample values Y(n) generated by sampling pulses in an analog signal from a magnetic read head positioned over the magnetic medium, said timing recovery method for adjusting the phase and frequency of a sampling clock signal relative to the phase and frequency of the pulse data, said timing recovery method comprising the steps of: (b) generating an a priori sequence of expected sample values X(n) corresponding to the discrete time sample values of a known acquisition preamble, wherein at least one of the expected sample values X(n) is generated independent from the discrete time sample values; and (a) generating a timing gradient value .increment.t(n) representing a minimum mean squared error between the discrete time sample values Y(n) and the corresponding a priori sequence of expected sample values X(n).
Claim 13
Dependent Claim
20 words
The timing recovery method as recited in claim 10 wherein the timing gradient value .increment.t(n) is computed as: .increment.t(n)=Y(n-1)·X(n)-Y(n)·X(n-1). 12.
Claim 14
Dependent Claim
31 words
The timing recovery method as recited in claim 10, wherein the expected sample values are generated first in response to the sign of two of the discrete time sample values Y(n).
Claim 15
Dependent Claim
34 words
The timing recovery method as recited in claim 10, wherein the expected sample values are generated first in response to the sign and absolute magnitude of two of the discrete time sample values Y(n).
Claim 16
Dependent Claim
96 words
The timing recovery method as recited in claim 10, wherein the expected sample values are generated by a discrete time counter comprising: (a) a clock input connected to the sampling clock; and (b) a discrete time output for outputting the counter value, representing the expected sample value, at the sampling clock rate, wherein the counter is loaded with a starting state value in response to a predetermined number of the discrete time sample values Y(n) and thereafter generates the expected sample values X(n) by sequencing through a plurality of predetermined states at each sample clock period.
Claim 17
Dependent Claim
96 words
The timing recovery method as recited in claim 10, wherein the timing recovery method is utilized in acquiring a known preamble of pulses in a substantially periodic form, wherein: (a) the expected sample values of the preamble are of the form +A,+A,-A,-A,+A,+A,-A,-A . . . ; and (b) the +A,+A values of the preamble correspond to a first pair of discrete values on each side, respectively, of the positive pulse peaks; and (c) the -A,-A values of the preamble correspond to a second pair of discrete values on each side, respectively, of the negative pulse peaks.
Claim 18
Dependent Claim
113 words
The timing recovery method as recited in claim 10, wherein the timing recovery circuit is utilized in acquiring a known preamble of pulses in a substantially periodic form, wherein: (a) the expected sample values of the preamble are of the form +A,0,-A,0,+A,0,-A,0. . . ; and (b) the +A values of the preamble correspond to a first discrete value at the peak of the positive pulses; and (c) the -A values of the preamble correspond to a second discrete value at the peak of the negative pulses; and (d) the 0 values of the preamble correspond to a third discrete time value at the beginning and ending of the positive and negative pulses.
Claim 19
Dependent Claim
117 words
The timing recovery method as recited in claim 10, further comprising the steps of: (a) generating a sequence of estimated sample values ˜X(n) in response to the discrete time sample values Y(n); and (b) transmitting to the timing gradient circuit the expected sample values X(n) during acquisition of a predetermined preamble, and the estimated sample values ˜X(n) during tracking of arbitrary data; and wherein the timing gradient value .increment.t(n) represents: a minimum mean squared error between the discrete time sample values Y(n) and the corresponding sequence of expected sample values X(n) during acquisition; and a minimum mean squared error between the discrete time sample values Y(n) and the corresponding sequence of estimated sample values ˜X(n) during tracking.
Claim 20
Dependent Claim
45 words
The timing recovery method as recited in claim 10, further comprising the steps of: (c) generating the sampling clock signal as the output of a variable frequency oscillator; and (d) adjusting the output of the variable frequency oscillator in response to the timing gradient .increment.t(n).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-18 | 2001-11-17 | 2002-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-18 | 2005-11-17 | 2006-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-18 | 2009-11-17 | 2010-05-19 | $7700.00 | Window Closed / Lapsed |