US5258933A
Expired / Lapsed
US
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Timing control for PRML class IV sampling data detection channel
Assignee: Maxtor Corp
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Filing: 1992-08-27
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Granted: 1993-11-02
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Expires: 2012-08-27
Abstract
Abstract A multi-mode timing loop for a PR4,ML sampled data channel includes an analog to digital converter and a digital finite impulse response filter for providing conditioned digital samples. The timing loop includes a reference clock source for putting out a reference clock frequency related to a nominal sample data rate, a frequency controllable oscillator connected to generate a sample clock, an analog timing loop and a digital timing loop. The analog timing loop provides phase lock during non-data read mode, and during data read mode the digital timing loop provides a vernier offset for fine adjustment of phase lock to a static setting then provided by the analog timing loop.
Inventors
- 👤 Kenneth E. Johnson
- 👤 William L. Abbott
- 👤 Hung C. Nguyen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:40
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054; G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; G11B20/10046; G11B20/10055; G11B20/10175; G11B20/12; G11B20/1217; G11B20/1258; G11B20/14; G11B20/1403; H04L7/04; H04L7/08; G11B2020/1264; G11B2020/1265; G11B2020/1281; G11B2020/1282; H04L7/041; H04L7/046; H04L7/10
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
327 words
A multi-mode timing loop for a PR4,ML sampled data channel including an analog to digital sampling and conversion means for providing raw digital samples of data at a sample clock rate and a digital finite impulse response filter means connected downstream of said analog to digital sampling and conversion means for providing conditioned digital samples at the sample clock rate, said timing loop comprising: reference clock source means for putting out a reference clock frequency related to a nominal sample clock rate for sampling data in said channel, controllable oscillator means for putting out a sample clock, an analog timing loop including: phase detector means for detecting and putting out a phase error between said reference clock frequency and said sample clock, charge pump means connected to receive said phase error and pump charge during a non-data read mode of operation of said multi-mode timing, loop, analog loop filter and charge storage means connected to receive charge pumped by said charge pump means during a non-data read mode and to filter and hold said charge during a data read mode of operation, said analog loop filter for putting out an analog timing control value to said controllable oscillator means, a digital timing loop including: timing error extraction means connected to receive said digital samples from said finite impulse response filter means for extracting timing error values therefrom, digital timing loop filter means for filtering said timing error values, and timing digital to analog converter means for converting said filtered timing error values into analog vernier timing correction values and for supplying said analog vernier timing correction values to said frequency controllable oscillator means during the data read mode, whereby the analog timing loop provides phase lock during non-data read mode and wherein during the data read mode the digital timing loop provides a vernier offset for fine adjustment of phase lock to a static setting provided by said analog timing loop at said frequency controllable oscillator means.
Claim 2
Dependent Claim
327 words
A multi-mode timing loop for a PR4,ML sampled data channel including an analog to digital sampling and conversion means for providing raw digital samples of data at a sample clock rate and a digital finite impulse response filter means connected downstream of said analog to digital sampling and conversion means for providing conditioned digital samples at the sample clock rate, said timing loop comprising: reference clock source means for putting out a reference clock frequency related to a nominal sample clock rate for sampling data in said channel, controllable oscillator means for putting out a sample clock, an analog timing loop including: phase detector means for detecting and putting out a phase error between said reference clock frequency and said sample clock, charge pump means connected to receive said phase error and pump charge during a non-data read mode of operation of said multi-mode timing, loop, analog loop filter and charge storage means connected to receive charge pumped by said charge pump means during a non-data read mode and to filter and hold said charge during a data read mode of operation, said analog loop filter for putting out an analog timing control value to said controllable oscillator means, a digital timing loop including: timing error extraction means connected to receive said digital samples from said finite impulse response filter means for extracting timing error values therefrom, digital timing loop filter means for filtering said timing error values, and timing digital to analog converter means for converting said filtered timing error values into analog vernier timing correction values and for supplying said analog vernier timing correction values to said frequency controllable oscillator means during the data read mode, whereby the analog timing loop provides phase lock during non-data read mode and wherein during the data read mode the digital timing loop provides a vernier offset for fine adjustment of phase lock to a static setting provided by said analog timing loop at said frequency controllable oscillator means.
Claim 3
Dependent Claim
48 words
The multi-mode timing loop set forth in claim 1 wherein the timing error extraction means is connected to receive raw data samples during an acquisition submode of said data read mode, and is connected to receive conditioned data samples during a tracking submode of said data read mode.
Claim 4
Dependent Claim
60 words
The multi-mode timing loop set forth in claim 2 wherein the timing error extractor circuit extracts during the acquisition submode the following timing error: z.sub.k.sup.a =-x.sub.k x.sub.k-1 +x.sub.k-1 x.sub.k and extracts during the tracking submode the following timing error: z.sub.k.sup.t =-y.sub.k y.sub.k-1 +y.sub.k-1 y.sub.k where x k represent raw data samples and y k represent filtered and conditioned data samples.
Claim 5
Dependent Claim
30 words
The multi-mode timing loop set forth in claim 2 wherein the digital timing loop filter means generates a filtered timing error during acquisition and tracking submodes as follows: αz.sub.k +Δ.sub.k.
Claim 6
Dependent Claim
45 words
The multi-mode timing loop set forth in claim 1 further comprising zero phase start mean s connected to stop and restart said controllable oscillator means in response to detected phase of an analog data stream received by said analog to digital sampling and conversion means.
Claim 7
Dependent Claim
86 words
The multi-mode timing loop set forth in claim 5 wherein said zero phase start means comprises analog comparator means connected to said analog data stream for comparing reference amplitude axis crossings of analog signals therein, and for putting out a start signal, zero phase start logic means connected to receive the start signal and put out the start control and variable delay means associated with the controllable oscillator means for stopping and then restarting operation thereof at a controllable instant following receipt of said start control.
Claim 8
Dependent Claim
55 words
The multi-mode timing loop set forth in claim 1 further comprising summing junction means for receiving and combining a control value related to said reference clock frequency, said analog timing error value and said analog vernier timing correction values into a sum thereof, and for supplying said sum to control said frequency controllable oscillator means.
Claim 9
Dependent Claim
23 words
The multi-mode timing loop set forth in claim 1 wherein said reference clock source comprises a programmable frequency synthesizer phase locked loop means.
Claim 10
Dependent Claim
50 words
The multi-mode timing loop set forth in claim 1 futher comprising an updata rate scaler means within the digital timing loop and wherein the update rate scaler means and the timing digital to analog converter means are clocked at a rate one half of the rate of the sample clock.
Claim 11
Dependent Claim
56 words
The multi-mode timing loop set forth in claim 9 wherein the update rate scaler means puts out to the timing digital to analog converter means the following: v.sub.k =1/2[(αz.sub.k +Δ.sub.k)+(αz.sub.k-1 +Δ.sub.k-1)] for one of even and odd filtered timing error values, and v.sub.k =v.sub.k-1 for the other of the even and odd filtered timing error values.
Claim 12
Independent Claim
219 words
A method for timing a PR4,ML sampled data channel including an analog to digital sampling and conversion means for providing raw digital samples of data at a sample clock rate and a digital finite impulse response filter means connected downstream of said analog to digital sampling and conversion means for providing conditioned digital samples at the sample clock rate, said timing method comprising the steps of: putting out a reference clock frequency related to a nominal sample clock rate for sampling data in said channel, generating and putting out a sample clock, detecting and putting out an analog phase error between said reference clock frequency and said sample clock, charging a storing means with a charge related to said phase error during a non-data read mode, filtering and converting said charge into an analog timing control value and applying said analog timing control value to control the frequency of said sample clock during the non-data read mode and during a data read mode, receiving said digital samples from said finite impulse response filter means and extracting timing error values therefrom, filtering said timing error values, and converting said filtered timing error values into analog vernier timing correction values and supplying said analog vernier timing correction values to adjust the frequency of said sample clock during the data read mode.
Claim 13
Independent Claim
219 words
A method for timing a PR4,ML sampled data channel including an analog to digital sampling and conversion means for providing raw digital samples of data at a sample clock rate and a digital finite impulse response filter means connected downstream of said analog to digital sampling and conversion means for providing conditioned digital samples at the sample clock rate, said timing method comprising the steps of: putting out a reference clock frequency related to a nominal sample clock rate for sampling data in said channel, generating and putting out a sample clock, detecting and putting out an analog phase error between said reference clock frequency and said sample clock, charging a storing means with a charge related to said phase error during a non-data read mode, filtering and converting said charge into an analog timing control value and applying said analog timing control value to control the frequency of said sample clock during the non-data read mode and during a data read mode, receiving said digital samples from said finite impulse response filter means and extracting timing error values therefrom, filtering said timing error values, and converting said filtered timing error values into analog vernier timing correction values and supplying said analog vernier timing correction values to adjust the frequency of said sample clock during the data read mode.
Claim 14
Dependent Claim
42 words
The method set forth in claim 11 comprising the further step of dividing said digital samples by a predetermined divisor and supplying a value related to a resultant quotient to adjust the frequency of said sample clock during the data read mode.
Claim 15
Dependent Claim
12 words
The method set forth in claim 12 wherein the divisor is two.
Claim 16
Dependent Claim
57 words
The method set forth in claim 11 further comprising the steps of: detecting a predetermined phase within an analog data stream received by said analog to digital sampling and conversion means, and stopping and restarting a controllable oscillator means generating said sample clock in response to the step of detecting said phase of the analog data stream.
Claim 17
Dependent Claim
50 words
The method set forth in claim 14 comprising the further steps of: comparing reference amplitude axis crossings of analog signals in said analog data stream and for putting out a start control, and stopping and then restarting operation of the controllable oscillator at a controllable instant following the start control.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-01 | 1997-05-03 | 1997-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-01 | 2001-05-03 | 2001-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-01 | 2005-05-03 | 2005-11-02 | $7700.00 | Window Closed / Lapsed |