Semiconductor memory device capable of controlling potential level of power supply line and/or ground line

Claim 2

A semiconductor memory device, comprising: a plurality of memory cells arranged in matrix of rows and columns; a plurality of word lines arranged for each row of said plurality of memory cells; a plurality of bit line pairs arranged for each column of said plurality of memory cells, each of said plurality of memory cells including a data storage portion holding data, and a data write/read portion performing write/read of data to/from said data storage portion, and said data storage portion having first and second inverter circuits connected in common to a power supply line arranged corresponding to respective columns of said plurality of memory cells; and a power supply line level control circuit controlling a potential level of said power supply line to a power supply potential or to a prescribed potential level lower than the power supply potential for each column in response to a level control signal set for each column.

Claim 3

The semiconductor memory device according to claim 1 , said power supply line level control circuit controls the potential level of said power supply line to said prescribed potential level for each column during a non-reading operation, and controls the potential level of said power supply line to the power supply potential with respect to a selected column and to said prescribed potential level with respect to a non-selected column respectively during a reading operation.

Claim 4

The semiconductor memory device according to claim 1 , wherein said power supply line level control circuit includes a plurality of power supply line level switching circuits provided for each column and switching the potential level of said power supply line to the power supply potential, a plurality of prescribed potential levels lower than the power supply potential, or floating for each column, in response to at least one of a retention test control signal, a redundancy replacement control signal, a plurality of retention potential setting signals, and said level control signal.

Claim 5

The semiconductor memory device according to claim 3 , wherein said power supply line level switching circuit switches the potential level of said power supply line to the power supply potential during access and retention test, switches the potential level of said power supply line to the power supply potential or said plurality of prescribed potential levels during non-access, and switches the potential level of said power supply line to floating during redundancy replacement.

Claim 6

The semiconductor memory device according to claim 4 , further comprising a setting signal control circuit controlling a logic level of said plurality of retention potential setting signals in synchronization with a clock signal in accordance with magnitude of the power supply potential.

Claim 7

The semiconductor memory device, according to claim 5 , wherein said setting signal control circuit includes a first potential level adjustment circuit outputting a first power supply potential shift signal having the potential level lower than the power supply potential by a prescribed value, in synchronization with said clock signal, a second potential level adjustment circuit outputting a second power supply potential shift signal having the potential level lower than said first potential level by a prescribed value, in synchronization with said clock signal, a first latch circuit outputting a first select control signal in accordance with a result obtained by comparison with an input threshold voltage, upon receiving said first power supply potential shift signal, and a second latch circuit outputting a second select control signal in accordance with a result obtained by comparison with said input threshold voltage, upon receiving said second power supply potential shift signal, and said setting signal control circuit controls the logic level of said plurality of retention potential setting signals in accordance with a combination of said first and second select control signals.