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JPH0973784A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device and its control circuit

Assignee: NEC Corp
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Filing: 1995-09-07
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Granted: —
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Expires: 2015-09-07
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Abstract

Abstract PROBLEM TO BE SOLVED: To eliminate that when a threshold voltage is lowered to make the operating speed of a MOS transistor fast, a stationary current becomes not to be ignored and then power consumption is increased. SOLUTION: This device is provided with a first power source line 101 being a high potential, a second power source line 102 being a low potential, a third power source line 103 capable of setting to the same potential as that of the first power source line 101 or to a potential lower a little than that of the line 101 and a fourth power source line 104 setabele to the same potential as that of the second power source line 102 or a potential higher a little than that of the line 102. Substrate terminal of pMOS transistors P1, P2 consisting of a static memory are connected to the first power source line 101 and the sources of transistors are connected to the third power source line 103 of respective substrate terminals and sources of nMOS transistors N1, N2 are respectively connected to the second power source line 102 and the fourth power source lines 104. At the time of a standby, a potential difference is made in between the first and the second power source lines and the third and the fourth power source lines and at the time of a driving are respectively made to equal potentials.

Inventors

  • 👤 Masayuki Mizuno
  • 👤 正之 水野

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-07 20:53
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412

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