US6881597B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device to provide a plurality of test element groups (TEGs) in a scribe region
Assignee: Renesas Electronics Corp
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Filing: 2002-01-22
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Granted: 2005-04-19
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Expires: 2022-01-22
Abstract
Abstract Disclosed is a technique capable of improving a yield of a semiconductor device by measuring a plurality of TEGs arranged in a scribe region. A first electrode pad connected to each terminal of a TEG is formed as a rectangular, minute, isolated pattern having a side length of about 0.5 μm or shorter and constituted of an uppermost layer wiring on a semiconductor substrate, and therefore, a great number of TEGs can be laid in a first scribe region. The characteristic evaluation or the failure analysis is performed by contacting a nanoprobe having a tip radius of curvature of 0.05 μm to 0.8 μm to the first electrode pad.
Inventors
- 👤 Kyoichiro Asayama
- 👤 Yasuhiro Mitsui
- 👤 Fumiko Arakawa
- 👤 Shiro Kamohara
- 👤 Yuzuru Ohji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 08:46
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/277
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
151 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a bonding pad and an extraction electrode each comprised of an uppermost layer wiring in a product circuit region; (b) forming a protection film on an upper layer of said uppermost layer wiring; and (c) partially exposing a surface of said bonding pad by removing a predetermined part of said protection film, wherein said uppermost layer wiring is formed by depositing a conductive body and then patterning by a lithography method, a plurality of logic circuits provided with said extraction electrode are formed in said product circuit region, and after partially exposing the surface of said extraction electrode by removing said protection film on said extraction electrode, a probe having a tip radius of curvature of about 0.05 μm to 0.8 μm is contacted to said extraction electrode, and then logic values of said logic circuits are evaluated.
Claim 2
Independent Claim
151 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a bonding pad and an extraction electrode each comprised of an uppermost layer wiring in a product circuit region; (b) forming a protection film on an upper layer of said uppermost layer wiring; and (c) partially exposing a surface of said bonding pad by removing a predetermined part of said protection film, wherein said uppermost layer wiring is formed by depositing a conductive body and then patterning by a lithography method, a plurality of logic circuits provided with said extraction electrode are formed in said product circuit region, and after partially exposing the surface of said extraction electrode by removing said protection film on said extraction electrode, a probe having a tip radius of curvature of about 0.05 μm to 0.8 μm is contacted to said extraction electrode, and then logic values of said logic circuits are evaluated.
Claim 3
Dependent Claim
33 words
The method of manufacturing a semiconductor device according to claim 1 ; wherein said protection film on said extraction electrode is removed by a focused ion beam method or a selective etching method.
Claim 4
Dependent Claim
42 words
The method of manufacturing a semiconductor device according to claim 1 ; wherein said logic circuit comprises n input terminals and m output terminals, and n+m+3 probes are contacted to said extraction electrodes to evaluate a logic value of said logic circuit.
Claim 5
Dependent Claim
23 words
The method of manufacturing a semiconductor device according to claim 3 , wherein one of said probes is a probe for contact confirmation.
Claim 6
Dependent Claim
21 words
The method of manufacturing a semiconductor device according to claim 1 , wherein said probe contains tungsten as a main component.
Claim 7
Dependent Claim
19 words
The method of manufacturing a semiconductor device according to claim 1 , wherein said logic circuits are TEG elements.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-04-18 | 2008-10-18 | 2009-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-04-18 | 2012-10-18 | 2013-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-04-18 | 2016-10-18 | 2017-04-19 | $7700.00 | Window Closed / Lapsed |