Semiconductor wafer and fabrication method of a semiconductor chip

Claim 1

A method of fabricating a plurality of semiconductor chips, comprising the sequential steps of: forming a wafer, wherein a plurality of semiconductor chip portions having internal circuits are disposed at regular intervals on the wafer and wherein a plurality of chip scribe lanes are formed between the semiconductor chip portions; forming a first insulating layer on the wafer; removing selected portions of the first insulating layer to expose portions of conductive lines in at least one chip scribe lane, wherein the conductive lines extend from at least one internal circuit of a semiconductor chip portion, the exposed portions of the conductive lines forming wafer probing pads; forming via holes in the first insulating layer to expose a portion of at least one internal circuit of a semiconductor chip portion; forming conductive regions in the via holes; forming a conductive layer that is electrically connected to the conductive regions in the via holes such that the conductive layer extends over a portion of a semiconductor chip portion; forming a second insulating layer on the first insulating layer and on the conductive layer, wherein portions of the conductive layer are exposed to form chip bonding pads; and cutting the wafer along the chip scribe lanes to form a plurality of semiconductor chips.

Claim 2

A method of fabricating a plurality of semiconductor chips, comprising the sequential steps of: forming a wafer, wherein a plurality of semiconductor chip portions having internal circuits are disposed at regular intervals on the wafer and wherein a plurality of chip scribe lanes are formed between the semiconductor chip portions; forming a first insulating layer on the wafer; removing selected portions of the first insulating layer to expose portions of conductive lines in at least one chip scribe lane, wherein the conductive lines extend from at least one internal circuit of a semiconductor chip portion, the exposed portions of the conductive lines forming wafer probing pads; forming via holes in the first insulating layer to expose a portion of at least one internal circuit of a semiconductor chip portion; forming conductive regions in the via holes; forming a conductive layer that is electrically connected to the conductive regions in the via holes such that the conductive layer extends over a portion of a semiconductor chip portion; forming a second insulating layer on the first insulating layer and on the conductive layer, wherein portions of the conductive layer are exposed to form chip bonding pads; and cutting the wafer along the chip scribe lanes to form a plurality of semiconductor chips.

Claim 6

A method of fabricating a plurality of semiconductor chips, comprising the steps of: forming a wafer, wherein a plurality of semiconductor chip portions having internal circuits are disposed at regular intervals on the wafer and wherein a plurality of chip scribe lanes are formed between the semiconductor chip portions; forming a first insulating layer on the wafer; removing selected portions of the first insulating layer to expose portions of conductive lines in at least one chip scribe lane, wherein the conductive lines extend from at least one internal circuit of a semiconductor chip portion, the exposed portions of the conductive lines forming wafer probing pads; forming chip bonding pads on the first insulating layer, the chip bonding pads extending over a portion of a semiconductor chip portion, the chip bonding pads being electrically coupled to at least one internal circuit of the semiconductor chip portion; forming a second insulating layer over the first insulating layer such that the second insulating layer covers the wafer probing pads, and such that the bonding pads remain exposed; and cutting the wafer along the chip scribe lanes to form a plurality of semiconductor chips.

Claim 7

A method of fabricating a plurality of semiconductor chips, comprising the steps of: forming a wafer, wherein a plurality of semiconductor chip portions having internal circuits are disposed at regular intervals on the wafer and wherein a plurality of chip scribe lanes are formed between the semiconductor chip portions; forming a first insulating layer on the wafer; removing selected portions of the first insulating layer to expose portions of conductive lines in at least one chip scribe lane, wherein the conductive lines extend from at least one internal circuit of a semiconductor chip portion, the exposed portions of the conductive lines forming wafer probing pads; forming chip bonding pads on the first insulating layer, the chip bonding pads extending over a portion of a semiconductor chip portion, the chip bonding pads being electrically coupled to at least one internal circuit of the semiconductor chip portion; forming a second insulating layer over the first insulating layer such that the second insulating layer covers the wafer probing pads, and such that the bonding pads remain exposed; and cutting the wafer along the chip scribe lanes to form a plurality of semiconductor chips.