Patent US6870226B2 successfully refreshed from Google Patents.
US6870226B2
Expired / Lapsed
US
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Semiconductor device and method of manufacturing same
Assignee: NEC Electronics Corp
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Filing: 2003-06-12
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Granted: 2005-03-22
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Expires: 2023-06-12
Abstract
Abstract There is provided a semiconductor device which is formed on a semiconductor substrate and allows effective use of the feature of the semiconductor substrate, and there is also provided a method of manufacturing the same. An N-channel MOS transistor including a P-type body layer ( 3 a ), and a P-type active layer ( 6 ) for body voltage application which is in contact with the P-type body layer ( 3 a ) are formed on an SOI substrate which is formed to align a <110> crystal direction of a support substrate ( 1 ) with a <100> crystal direction of an SOI layer ( 3 ). A path connecting the P-type body layer ( 3 a ) and the P-type active layer ( 6 ) for body voltage application is aligned parallel to the <100> crystal direction of the SOI layer ( 3 ). Since hole mobility is higher in the <100> crystal direction, parasitic resistance (Ra, Rb) can be reduced in the above path. This speeds up voltage transmission to the P-type body layer ( 3 a ) and improves voltage fixing capability in the P-type body layer ( 3 a ).
Inventors
- 👤 Shigenobu Maeda
- 👤 Shigeto Maegawa
- 👤 Takuji Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:37
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6704; H10D30/6708; H10D30/6711; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D30/6748; H10D30/6758; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/378; H10D62/40; H10D62/405; H10D86/201; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10D30/6713; H10D30/6715; H10D30/6757
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
153 words
A semiconductor device comprising: an SOI (Semiconductor On Insulator) substrate in which a support substrate, an oxide film layer, and an SOI layer are stacked in this order, said support substrate and said SOI layer having different crystal orientations with respect to each other; an N-channel MIS (Metal Insulator Semiconductor) transistor including a gate insulating film formed on said SOI layer, a gate electrode formed on said gate insulating film, an N-type source/drain active layer formed adjacent to said gate electrode in said SOI layer, and a P-type body layer formed at least under said gate electrode in said SOI layer; and a P-type active layer for body voltage application which is formed in said SOI layer and in contact with said P-type body layer, wherein a path connecting said P-type body layer and said P-type active layer for body voltage application is aligned parallel to a crystal direction of said SOI layer.
Claim 2
Dependent Claim
153 words
A semiconductor device comprising: an SOI (Semiconductor On Insulator) substrate in which a support substrate, an oxide film layer, and an SOI layer are stacked in this order, said support substrate and said SOI layer having different crystal orientations with respect to each other; an N-channel MIS (Metal Insulator Semiconductor) transistor including a gate insulating film formed on said SOI layer, a gate electrode formed on said gate insulating film, an N-type source/drain active layer formed adjacent to said gate electrode in said SOI layer, and a P-type body layer formed at least under said gate electrode in said SOI layer; and a P-type active layer for body voltage application which is formed in said SOI layer and in contact with said P-type body layer, wherein a path connecting said P-type body layer and said P-type active layer for body voltage application is aligned parallel to a crystal direction of said SOI layer.
Claim 3
Dependent Claim
50 words
The semiconductor device according to claim 1 , further comprising: an element isolation region of a partial isolation type which is an element isolation region for isolating said N-channel MIS transistor and which does not extend to said oxide film layer in a direction of thickness of said SOI layer.
Claim 4
Dependent Claim
41 words
The semiconductor device according to claim 1 , wherein said gate electrode includes a contact plug connection, and a portion of said gate insulating film which is located under said contact plug connection has a thickness greater than the other portion.
Claim 5
Dependent Claim
27 words
The semiconductor device according to claim 1 , wherein said P-type active layer for body voltage application is located in part of said N-type source/drain active layer.
Claim 6
Dependent Claim
23 words
The semiconductor device according to claim 1 , wherein said P-type active layer for body voltage application and said gate electrode are short-circuited.
Claim 7
Dependent Claim
127 words
A semiconductor device comprising: an SOI (Semiconductor On Insulator) substrate in which a support substrate, an oxide film layer, and an SOI layer are stacked in this order, said support substrate and said SOI layer having different crystal orientations with respect to each other; an MIS (Metal Insulator Semiconductor) capacitor including a gate insulating film formed on said SOI layer, a gate electrode formed on said gate insulating film, and a P-type body layer formed at least under said gate electrode within said SOI layer; and a P-type active layer formed in said SOI layer and electrically connected to said P-type body layer, wherein a path connecting said P-type body layer and said P-type active layer is aligned parallel to a crystal direction of said SOI layer.
Claim 8
Dependent Claim
127 words
A semiconductor device comprising: an SOI (Semiconductor On Insulator) substrate in which a support substrate, an oxide film layer, and an SOI layer are stacked in this order, said support substrate and said SOI layer having different crystal orientations with respect to each other; an MIS (Metal Insulator Semiconductor) capacitor including a gate insulating film formed on said SOI layer, a gate electrode formed on said gate insulating film, and a P-type body layer formed at least under said gate electrode within said SOI layer; and a P-type active layer formed in said SOI layer and electrically connected to said P-type body layer, wherein a path connecting said P-type body layer and said P-type active layer is aligned parallel to a crystal direction of said SOI layer.
Claim 9
Dependent Claim
141 words
A semiconductor device comprising: an SOI (Semiconductor On Insulator) substrate in which a support substrate, an oxide film layer, and an SOI layer are stacked in this order, said support substrate and said SOI layer having different crystal orientations with respect to each other; an MIS (Metal Insulator Semiconductor) transistor including a gate insulating film formed on said SOI layer, a gate electrode formed on said gate insulating film, and a source/drain active layer formed adjacent to said gate electrode in said SOI layer; and another device formed on said SOI layer, wherein the source and the gate of said MIS transistor are short-circuited, the drain of said MIS transistor is connected to a signal input or output of said another device, and a channel direction in said MIS transistor is aligned parallel to a crystal direction of said MIS transistor.
Claim 10
Dependent Claim
141 words
A semiconductor device comprising: an SOI (Semiconductor On Insulator) substrate in which a support substrate, an oxide film layer, and an SOI layer are stacked in this order, said support substrate and said SOI layer having different crystal orientations with respect to each other; an MIS (Metal Insulator Semiconductor) transistor including a gate insulating film formed on said SOI layer, a gate electrode formed on said gate insulating film, and a source/drain active layer formed adjacent to said gate electrode in said SOI layer; and another device formed on said SOI layer, wherein the source and the gate of said MIS transistor are short-circuited, the drain of said MIS transistor is connected to a signal input or output of said another device, and a channel direction in said MIS transistor is aligned parallel to a crystal direction of said MIS transistor.
Claim 11
Dependent Claim
165 words
A semiconductor device comprising: an SOI (Semiconductor On Insulator) substrate in which a support substrate, an oxide film layer, and an SOI layer are stacked in this order, said support substrate and said SOI layer having different crystal orientations with respect to each other; and an MIS (Metal Insulator Semiconductor) transistor including a gate insulating film formed on said SOI layer, a gate electrode formed on said gate insulating film, and a source/drain active layer formed adjacent to said gate electrode in said SOI layer, wherein by forming a first semiconductor layer in a channel forming region in said SOI layer where a channel is formed and forming a second semiconductor layer in an adjacent region of said channel forming region in said SOI layer, a lattice constant of said first semiconductor layer is made approximately equal to a lattice constant of said second semiconductor layer, and a channel direction in said MIS transistor is aligned parallel to a crystal direction of said SOI layer.
Claim 12
Dependent Claim
165 words
A semiconductor device comprising: an SOI (Semiconductor On Insulator) substrate in which a support substrate, an oxide film layer, and an SOI layer are stacked in this order, said support substrate and said SOI layer having different crystal orientations with respect to each other; and an MIS (Metal Insulator Semiconductor) transistor including a gate insulating film formed on said SOI layer, a gate electrode formed on said gate insulating film, and a source/drain active layer formed adjacent to said gate electrode in said SOI layer, wherein by forming a first semiconductor layer in a channel forming region in said SOI layer where a channel is formed and forming a second semiconductor layer in an adjacent region of said channel forming region in said SOI layer, a lattice constant of said first semiconductor layer is made approximately equal to a lattice constant of said second semiconductor layer, and a channel direction in said MIS transistor is aligned parallel to a crystal direction of said SOI layer.
References Cited (Backward Citations)
JPH07335511A
Cited
JP2002134374A
Cited
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