US6865701B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for improved memory core testing
Assignee: Apple Inc
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Filing: 2001-03-29
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Granted: 2005-03-08
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Expires: 2021-03-29
Abstract
Abstract A memory unit is described that has a controller coupled to a memory core through an interface circuit. The interface circuit has a test data input that receives test data from the controller. The interface circuit also has a system data input that receives data from a system. The interface circuit has a data output that is coupled to a data input of the memory core.
Inventors
- 👤 Lynn R. Youngs
- 👤 Derek F. Iwamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:01
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/1201; G11C29/14; G11C29/48; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
238 words
A semiconductor chip, comprising: a) a multi-ported memory having a plurality of data input ports; b) a controller to execute test commands to test said multi-ported memory; and, c) an interface circuit to interface said data input ports to both said controller and a system that uses said memory, said interface circuit comprising a group of three circuit paths for each one of said memory input ports, each circuit path of said group of three circuit paths to transport data to be written into said memory, each said group of three circuit paths comprising: i) a first circuit path that flows from said system to a data input port that said first circuit path's group of three circuit paths are associated with, said first circuit path to transport data provided by said system; ii) a second circuit path that flows from said controller to said data input port, said second circuit path to transport first test data provided by said controller; iii) a third circuit path that flows from said controller to register circuitry and from said register circuitry to said data input port, a portion of said third circuit path that precedes said register circuitry to transport second test data provided by said controller, a portion of said third circuit path that follows said register circuitry to transport said second test data after it has already been transported into said memory by another group's second circuit path.
Claim 2
Dependent Claim
238 words
A semiconductor chip, comprising: a) a multi-ported memory having a plurality of data input ports; b) a controller to execute test commands to test said multi-ported memory; and, c) an interface circuit to interface said data input ports to both said controller and a system that uses said memory, said interface circuit comprising a group of three circuit paths for each one of said memory input ports, each circuit path of said group of three circuit paths to transport data to be written into said memory, each said group of three circuit paths comprising: i) a first circuit path that flows from said system to a data input port that said first circuit path's group of three circuit paths are associated with, said first circuit path to transport data provided by said system; ii) a second circuit path that flows from said controller to said data input port, said second circuit path to transport first test data provided by said controller; iii) a third circuit path that flows from said controller to register circuitry and from said register circuitry to said data input port, a portion of said third circuit path that precedes said register circuitry to transport second test data provided by said controller, a portion of said third circuit path that follows said register circuitry to transport said second test data after it has already been transported into said memory by another group's second circuit path.
Claim 3
Dependent Claim
53 words
The semiconductor chip of claim 1 wherein said interface circuit further comprises a multiplexer comprising: a) a channel select input coupled to an output of said controller; b) an input through which only one of said circuit paths flow; and, c) an output through which more than one of said circuit paths flow.
Claim 4
Dependent Claim
15 words
The semiconductor chip of claim 1 wherein said test commands comprise a PRELOAD WRITE command.
Claim 5
Dependent Claim
15 words
The semiconductor chip of claim 1 wherein said test commands comprise a PRELOAD READ command.
Claim 6
Dependent Claim
14 words
The semiconductor chip of claim 1 wherein said test commands comprise a WRITE command.
Claim 7
Dependent Claim
24 words
The semiconductor chip of claim 5 wherein said WRITE command has a field to indicate less than a full word is to be written.
Claim 8
Dependent Claim
14 words
The semiconductor chip of claim 1 wherein said test commands comprise a READ command.
Claim 9
Dependent Claim
24 words
The semiconductor chip of claim 7 wherein said READ command has a field to indicate less than a full word is to be read.
Claim 10
Dependent Claim
25 words
The semiconductor chip of claim 1 wherein said controller comprises an output to send a command to a downstream controller in a daisy chain configuration.
Claim 11
Dependent Claim
33 words
The semiconductor chip of claim 9 wherein said controller comprises a transparent mode in which test commands received by said controller are: not executed by said controller; and forwarded to said downstream controller.
Claim 12
Dependent Claim
26 words
The semiconductor chip of claim 10 wherein said controller comprises a selected mode in which test commands received by said controller are executed by said controller.
Claim 13
Dependent Claim
23 words
The semiconductor chip of claim 11 wherein said controller, while in said selected mode, also forwards received test commands to said downstream controller.
Claim 14
Independent Claim
205 words
A method, comprising: (i) while testing a multi-ported memory: a) issuing test data from a controller to be written into said multi-ported memory: from at least one data input port of said multi-ported memory, but not, from all data input ports of said multi-ported memory; b) writing said test data into said multi-ported memory from said at least one data input port of said multi-ported memory, and, for each of said data input ports of said multi-ported memory that said writing is not applied to: storing said test data into register circuitry; c) for at least one of said data input ports of said multi-ported memory that said writing is not applied to: reading said test data from said register circuitry, and, writing said test data into said multi-ported memory from said at least one data input port of said data input ports that said writing of b) was not applied to; and, (ii) while operating a system that uses said multi-ported memory: writing data into a particular data input port of said multi-ported memory, said data flowing through a multiplexer through which said test data flowed prior to said test data being said written into said multi-ported memory from said particular data input port.
Claim 15
Independent Claim
205 words
A method, comprising: (i) while testing a multi-ported memory: a) issuing test data from a controller to be written into said multi-ported memory: from at least one data input port of said multi-ported memory, but not, from all data input ports of said multi-ported memory; b) writing said test data into said multi-ported memory from said at least one data input port of said multi-ported memory, and, for each of said data input ports of said multi-ported memory that said writing is not applied to: storing said test data into register circuitry; c) for at least one of said data input ports of said multi-ported memory that said writing is not applied to: reading said test data from said register circuitry, and, writing said test data into said multi-ported memory from said at least one data input port of said data input ports that said writing of b) was not applied to; and, (ii) while operating a system that uses said multi-ported memory: writing data into a particular data input port of said multi-ported memory, said data flowing through a multiplexer through which said test data flowed prior to said test data being said written into said multi-ported memory from said particular data input port.
Claim 16
Dependent Claim
41 words
The method of claim 13 wherein said at least one of said data input ports that said writing of b) was not applied to further comprises all of said data input ports that said writing of b) was not applied to.
Claim 17
Dependent Claim
47 words
The method of claim 13 further comprising: sending test commands to said controller; sending said test commands from said controller to a next controller in a daisy chain configuration; using said test commands to test a second multi ported memory that said next controller is coupled to.
Claim 18
Dependent Claim
176 words
The method of claim 15 wherein said testing of said second multi-ported memory further comprises: d) issuing second test data from said next controller to be written into said second multi-ported memory: from at least one data input port of said second multi-ported memory, but not, from all data input ports of said second multi-ported memory; e) writing said second test data into said second multi-ported memory from said at least one data input port of said second multi-ported memory, and, for each of said data input ports of said second multi-ported memory that said writing is not applied to: storing said test data into second register circuitry; and, f) for at least one of said data input ports of said second multi-ported memory that said writing of e) is not applied to: reading said second test data from said second register circuitry, and, writing said second test data into said second multi-ported memory from said at least one data input port of said data input ports that said writing of e) was not applied to.
Claim 19
Dependent Claim
66 words
The method of claim 16 further comprising, while operating a system that uses said second multi-ported memory, writing second data into a particular data input port of said second multi-ported memory, said second data flowing through a second multiplexer through which said second test data flowed prior to said second test data being said written into said second multi-ported memory from said particular data input port.
Claim 20
Dependent Claim
37 words
The method of claim 16 further comprising sending a command to said controller prior to said sending test commands to said controller that cause said controller to enter a transparent mode and not execute said test commands.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2008-03-07 | 2008-09-06 | 2009-03-08 | $2000.00 | Window Closed / Lapsed |
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