Phase/frequency detector and phase lock loop circuit

Claim 2

A cycle slip detector circuit comprising: a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means.

Claim 3

A circuit according to claim 1 wherein the delay means is embedded in the circuitry of the third and fourth latches or in the first and second latches or in a combination.

Claim 4

A circuit according to claim 2 wherein the third and fourth latches each comprise an addition circuit stage on the input coupled to the respective control signal output.

Claim 5

A circuit according to claim 1 wherein the delay means comprises separate circuit elements between the first and third and the second and fourth latches respectively.

Claim 6

A circuit according to claim 4 wherein the separate circuit elements comprise a logic device.

Claim 7

A circuit according to claim 1 wherein the predetermined delay is less than the remainder of the input signal period less the reset time of the phase and frequency detector circuit.

Claim 8

A circuit according to claim 1 wherein the predetermined delay is sufficient to delay an output signal from the first or second latches to the respective third or fourth latches input until said third or fourth latches output signal has responded to the first or second input signal to which said output signal responded.

Claim 9

A circuit according to claim 7 wherein the first and second latches are fast flip flop circuits.

Claim 10

A circuit according to claim 8 wherein said fast flip flop circuits are NOR or NAND gate pairs.

Claim 11

A circuit according to claim 7 wherein the third and fourth latches are slow latch circuits.

Claim 12

A circuit according to claim 10 wherein the slow latch circuits are D-type flip flops.

Claim 13

A lock detector circuit for a phase lock loop having a phase and frequency detector; the lock detector comprising: a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means; and a circuit arranged to indicate lock when output signals indicating a cycle slip from the third or fourth latches have not been asserted for a predetermined time.

Claim 14

A lock detector circuit for a phase lock loop having a phase and frequency detector; the lock detector comprising: a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means; and a circuit arranged to indicate lock when output signals indicating a cycle slip from the third or fourth latches have not been asserted for a predetermined time.

Claim 15

A circuit according to claim 12 wherein the predetermined delay is sufficient to delay an output signal from the first or second latches to the respective third or fourth latches input until said third or fourth latches output signal has responded to the first or second input signal to which said output signal responded.

Claim 16

A circuit according to claim 12 wherein the lock indication circuit comprises combining circuit for logically combining the outputs of said third and fourth latches, and a timer circuit coupled to the output of said combining circuit.

Claim 17

A circuit according to claim 12 wherein the predetermined time is approximately the predicted post-cycle-slip settling time of the loop.

Claim 18

A circuit according to claim 15 wherein the predetermined time is approximately 2 pi/wn.

Claim 19

A phase or frequency mode indicator circuit for a phase lock loop, the circuit comprising: a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means; a circuit arranged to indicate a phase or frequency mode dependent on whether said cycle slip detector circuit indicates cycle slips.

Claim 20

A phase or frequency mode indicator circuit for a phase lock loop, the circuit comprising: a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means; a circuit arranged to indicate a phase or frequency mode dependent on whether said cycle slip detector circuit indicates cycle slips.

Claim 21

A phase lock loop circuit comprising a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means.

Claim 22

A phase lock loop circuit comprising a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means.

Claim 23

A phase lock loop circuit comprising a lock detector circuit comprising: a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means; a circuit arranged to indicate lock when output signals indicating a cycle slip from the third or fourth latches have not been asserted for a predetermined time.

Claim 24

A phase lock loop circuit comprising a lock detector circuit comprising: a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means; a circuit arranged to indicate lock when output signals indicating a cycle slip from the third or fourth latches have not been asserted for a predetermined time.

Claim 25

A phase lock loop circuit comprising a phase of frequency mode indicator circuit comprising: a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means; a circuit arranged to indicate phase or frequency mode dependent on whether said cycle slip detector indicates cycle slips.

Claim 26

A phase lock loop circuit comprising a phase of frequency mode indicator circuit comprising: a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means; a circuit arranged to indicate phase or frequency mode dependent on whether said cycle slip detector indicates cycle slips.

Claim 27

A clock frequency synthesiser comprising a phase lock loop circuit comprising a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means.

Claim 28

A clock frequency synthesiser comprising a phase lock loop circuit comprising a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means.

Claim 29

Digital audio apparatus comprising a phase lock loop circuit comprising a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means.

Claim 30

Digital audio apparatus comprising a phase lock loop circuit comprising a cycle slip detector circuit comprising a phase and frequency detector circuit having first and second latches each having an input for receiving respective first and second input signals and arranged to provide respective first and second control signal outputs responsive to a predetermined part of the waveform of the first or second input signals; third and fourth latches each having a first input coupled to a respective control signal output and a second input coupled to the respective first or second latch, input corresponding to said control signal output; delay means arranged to provide a predetermined delay between each said control signal and the respective third or fourth latch means.