Frequency acquisition circuit and method for a phase locked loop

Claim 2

A circuit for aiding proper frequency lock in a phase locked loop, comprising: a phase detector adapted for receiving an input signal and an oscillator output signal from the phase locked loop and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal; an up cycle slip detector latching the up pulse width modulated cycle slip signal with the input signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal; a down cycle slip detector latching the down pulse width modulated cycle slip signal with the oscillator output signal and generating a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal; and a phase correction circuit generating a steering signal in response to the up and down cycle slip signals, the phase correction circuit including a cycle slip circuit receiving the up and down cycle slip signals and including a cycle slip counter for generating an UP 2 signal in response to receiving two consecutive up cycle slip signals or generating a DOWN 2 signal in response to receiving two consecutive down cycle slip signals, and an OR gate receiving the UP 2 and DOWN 2 signals and generating a cycle slip signal for selectively connecting or disconnecting a steering signal to the phase locked loop; and a fixed up/down counter receiving the up and down cycle slip signals and being adapted for generating the steering signal indicative of the amount of correction desired.

Claim 3

The circuit, as set forth in claim 1 , wherein the phase correction circuit further comprises a digital to analog converter coupled to the fixed up/down counter being adapted for converting the steering signal into a steering current.

Claim 4

The circuit, as set forth in claim 1 , wherein the cycle slip circuit comprises a cycle slip counter for counting a predetermined number of consecutive up cycle slip signals or a predetermined number of consecutive down cycle slip signals being received.

Claim 5

The circuit, as set forth in claim 1 , wherein the phase correction circuit comprises a state machine.

Claim 6

The circuit, as set forth in claim 1 , wherein the up cycle slip detector comprises: a latch adapted for latching the up pulse width modulated cycle slip signal with the input signal; and a logic circuit adapted for receiving the latched up pulse width modulated cycle slip signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal.

Claim 7

The circuit, as set forth in claim 1 , wherein the down cycle slip detector comprises: a latch adapted for latching the down pulse width modulated cycle slip signal with the oscillator output signal; and a logic circuit adapted for receiving the latched down pulse width modulated cycle slip signal and generating a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal.

Claim 8

A circuit for aiding proper frequency lock in a phase locked loop, comprising: a phase detector adapted for receiving an input signal and an oscillator output signal from the phase locked loop and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal; an up cycle slip detector latching the up pulse width modulated cycle slip signal with the input signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal; a down cycle slip detector latching the down pulse width modulated cycle slip signal with the oscillator output signal and generating a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal; and a phase correction circuit generating a steering signal in response to the up and down cycle slip signals, wherein the phase correction circuit comprises: a first D flip-flop coupled to the first logic circuit and receiving the up cycle slip signal clocked by the input signal; a first NAND gate coupled to the output of the first D flip-flop and also receiving an inverted up cycle slip signal; a first latch receiving an output of the first NAND gate and the down cycle slip signal and generating an UP 2 signal; a second D flip-flop coupled to the second logic circuit and receiving the down cycle slip signal clocked by the oscillator output signal; a second NAND gate coupled to the output of the second D flip-flop and also receiving an inverted down cycle slip signal; and a second latch receiving an output of the second NAND gate and the up cycle slip signal and generating a DOWN 2 signal.

Claim 9

A circuit for aiding proper frequency lock in a phase locked loop, comprising: a phase detector adapted for receiving an input signal and an oscillator output signal from the phase locked loop and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal; an up cycle slip detector latching the up pulse width modulated cycle slip signal with the input signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal; a down cycle slip detector latching the down pulse width modulated cycle slip signal with the oscillator output signal and generating a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal; and a phase correction circuit generating a steering signal in response to the up and down cycle slip signals, wherein the phase correction circuit comprises: a first D flip-flop coupled to the first logic circuit and receiving the up cycle slip signal clocked by the input signal; a first NAND gate coupled to the output of the first D flip-flop and also receiving an inverted up cycle slip signal; a first latch receiving an output of the first NAND gate and the down cycle slip signal and generating an UP 2 signal; a second D flip-flop coupled to the second logic circuit and receiving the down cycle slip signal clocked by the oscillator output signal; a second NAND gate coupled to the output of the second D flip-flop and also receiving an inverted down cycle slip signal; and a second latch receiving an output of the second NAND gate and the up cycle slip signal and generating a DOWN 2 signal.

Claim 10

The circuit, as set forth in claim 7 , wherein the phase correction circuit comprises: a cycle slip circuit receiving the up and down cycle slip signals and being adapted for generating a cycle slip signal in response to a predetermined number of consecutive up or down cycle slip signals being received; and a fixed up/down counter receiving the up and down cycle slip signals and being adapted for generating a steering signal indicative of the amount of correction desired.

Claim 11

The circuit, as set forth in claim 8 , wherein the phase correction circuit further comprises a digital to analog converter coupled to the fixed up/down counter being adapted for converting the steering signal into a steering current.

Claim 12

The circuit, as set forth in claim 8 , wherein the cycle slip circuit comprises a cycle slip counter for counting a predetermined number of consecutive up cycle slip signals or a predetermined number of consecutive down cycle slip signals being received.

Claim 13

The circuit, as set forth in claim 7 , wherein the phase correction circuit comprises a state machine.

Claim 14

The circuit, as set forth in claim 7 , wherein the up cycle slip detector comprises: a latch adapted for latching the up pulse width modulated cycle slip signal with the input signal; and a logic circuit adapted for receiving the latched up pulse width modulated cycle slip signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal.

Claim 15

The circuit, as set forth in claim 7 , wherein the down cycle slip detector comprises: a latch adapted for latching the down pulse width modulated cycle slip signal with the oscillator output signal; and a logic circuit adapted for receiving the latched down pulse width modulated cycle slip signal and generating a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal.

Claim 16

A circuit for aiding proper frequency lock in a phase locked loop, comprising: a phase detector adapted for receiving an input signal and an oscillator output signal from the phase locked loop and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal, wherein the phase detector comprises: a first RS latch receiving the input signal at its set input; a second RS latch receiving the inverted output of the first RS latch at its reset input; a third RS latch receiving the oscillator output signal at its set input; a fourth RS latch receiving the inverted output of the first RS latch at its reset input; a NAND gate coupled to the non-inverted outputs of the second and fourth RS latches, and the inverted outputs of the first and third RS latches, and generating an output; the output from the NAND gate further being coupled to the set inputs of the second and fourth RS latches; a first AND gate being coupled to the inverted output of the first RS latch and the output of the NAND gate, the output of the first AND gate being coupled to the reset input of the first RS latch; a second AND gate being coupled to the inverted output of the third RS latch and the output of the NAND gate, the output of the second AND gate being coupled to the reset input of the third RS latch; and the up pulse width modulated cycle slip signal being the inverted output of the first RS latch, and the down pulse width modulated cycle slip signal being the inverted output of the third RS latch; an up cycle slip detector latching the up pulse width modulated cycle slip signal with the input signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal; a down cycle slip detector latching the down pulse width modulated cycle slip signal with the oscillator output signal and generating a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal; and a phase correction circuit generating a steering signal in response to the up and down cycle slip signals.

Claim 17

A circuit for aiding proper frequency lock in a phase locked loop, comprising: a phase detector adapted for receiving an input signal and an oscillator output signal from the phase locked loop and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal, wherein the phase detector comprises: a first RS latch receiving the input signal at its set input; a second RS latch receiving the inverted output of the first RS latch at its reset input; a third RS latch receiving the oscillator output signal at its set input; a fourth RS latch receiving the inverted output of the first RS latch at its reset input; a NAND gate coupled to the non-inverted outputs of the second and fourth RS latches, and the inverted outputs of the first and third RS latches, and generating an output; the output from the NAND gate further being coupled to the set inputs of the second and fourth RS latches; a first AND gate being coupled to the inverted output of the first RS latch and the output of the NAND gate, the output of the first AND gate being coupled to the reset input of the first RS latch; a second AND gate being coupled to the inverted output of the third RS latch and the output of the NAND gate, the output of the second AND gate being coupled to the reset input of the third RS latch; and the up pulse width modulated cycle slip signal being the inverted output of the first RS latch, and the down pulse width modulated cycle slip signal being the inverted output of the third RS latch; an up cycle slip detector latching the up pulse width modulated cycle slip signal with the input signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal; a down cycle slip detector latching the down pulse width modulated cycle slip signal with the oscillator output signal and generating a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal; and a phase correction circuit generating a steering signal in response to the up and down cycle slip signals.

Claim 18

The circuit, as set forth in claim 14 , wherein the phase correction circuit comprises: a cycle slip circuit receiving the up and down cycle slip signals and being adapted for generating a cycle slip signal in response to a predetermined number of consecutive up or down cycle slip signals being received; and a fixed up/down counter receiving the up and down cycle slip signals and being adapted for generating a steering signal indicative of the amount of correction desired.

Claim 19

The circuit, as set forth in claim 15 , wherein the phase correction circuit further comprises a digital to analog converter coupled to the fixed up/down counter being adapted for converting the steering signal into a steering current.

Claim 20

The circuit, as set forth in claim 15 , wherein the cycle slip circuit comprises a cycle slip counter for counting a predetermined number of consecutive up cycle slip signals or a predetermined number of consecutive down cycle slip signals being received.

Claim 21

The circuit, as set forth in claim 14 , wherein the phase correction circuit comprises a state machine.

Claim 22

The circuit, as set forth in claim 14 , wherein the up cycle slip detector comprises: a latch adapted for latching the up pulse width modulated cycle slip signal with the input signal; and a logic circuit adapted for receiving the latched up pulse width modulated cycle slip signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal.

Claim 23

The circuit, as set forth in claim 14 , wherein the down cycle slip detector comprises: a latch adapted for latching the down pulse width modulated cycle slip signal with the oscillator output signal; and a logic circuit adapted for receiving the latched down pulse width modulated cycle slip signal and generating a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal.

Claim 24

A circuit for aiding proper frequency lock in a phase locked loop, comprising: a phase detector adapted for receiving an input signal and an oscillator output signal from the phase locked loop and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal; a first latch adapted for latching the up pulse width modulated cycle slip signal with the input signal; a first logic circuit adapted for receiving the latched up pulse width modulated cycle slip signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal; a second latch adapted for latching the down pulse width modulated cycle slip signal with the oscillator output signal; a second logic circuit adapted for receiving the latched down pulse width modulated cycle slip signal and generating a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal; and a phase correction circuit generating a steering signal in response to the up and down cycle slip signals, wherein the phase correction circuit comprises: a first D flip-flop coupled to the first logic circuit and receiving the up cycle slip signal clocked by the input signal; a first NAND gate coupled to the output of the first D flip-flop and also receiving an inverted up cycle slip signal; a first latch receiving an output of the first NAND gate and the down cycle slip signal and generating an UP 2 signal; a second D flip-flop coupled to the second logic circuit and receiving the down cycle slip signal clocked by the oscillator output signal; a second NAND gate coupled to the output of the second D flip-flop and also receiving an inverted down cycle slip signal; and a second latch receiving an output of the second NAND gate and the up cycle slip signal and generating a DOWN 2 signal.

Claim 25

A circuit for aiding proper frequency lock in a phase locked loop, comprising: a phase detector adapted for receiving an input signal and an oscillator output signal from the phase locked loop and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal; a first latch adapted for latching the up pulse width modulated cycle slip signal with the input signal; a first logic circuit adapted for receiving the latched up pulse width modulated cycle slip signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal; a second latch adapted for latching the down pulse width modulated cycle slip signal with the oscillator output signal; a second logic circuit adapted for receiving the latched down pulse width modulated cycle slip signal and generating a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal; and a phase correction circuit generating a steering signal in response to the up and down cycle slip signals, wherein the phase correction circuit comprises: a first D flip-flop coupled to the first logic circuit and receiving the up cycle slip signal clocked by the input signal; a first NAND gate coupled to the output of the first D flip-flop and also receiving an inverted up cycle slip signal; a first latch receiving an output of the first NAND gate and the down cycle slip signal and generating an UP 2 signal; a second D flip-flop coupled to the second logic circuit and receiving the down cycle slip signal clocked by the oscillator output signal; a second NAND gate coupled to the output of the second D flip-flop and also receiving an inverted down cycle slip signal; and a second latch receiving an output of the second NAND gate and the up cycle slip signal and generating a DOWN 2 signal.

Claim 26

The circuit, as set forth in claim 21 , wherein the phase correction circuit comprises: a cycle slip circuit receiving the up and down cycle slip signals and being adapted for generating a cycle slip signal in response to a predetermined number of consecutive up or down cycle slip signals being received; and a fixed up/down counter receiving the up and down cycle slip signals and being adapted for generating a steering signal indicative of the amount of correction desired.

Claim 27

The circuit, as set forth in claim 22 , wherein the cycle slip circuit comprises a cycle slip counter for counting a predetermined number of consecutive up cycle slip signals or a predetermined number of consecutive down cycle slip signals being received.

Claim 28

The circuit, as set forth in claim 22 , wherein the phase correction circuit further comprises a digital to analog converter coupled to the fixed up/down counter being adapted for converting the steering signal into a steering current.

Claim 29

The circuit, as set forth in claim 21 , wherein the phase correction circuit comprises a state machine.

Claim 30

The circuit, as set forth in claim 21 , wherein the up cycle slip detector comprises: a latch adapted for latching the up pulse width modulated cycle slip signal with the input signal; and a logic circuit adapted for receiving the latched up pulse width modulated cycle slip signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal.

Claim 31

The circuit, as set forth in claim 21 , wherein the down cycle slip detector comprises: a latch adapted for latching the down pulse width modulated cycle slip signal with the oscillator output signal; and a logic circuit adapted for receiving the latched down pulse width modulated cycle slip signal and generating a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal.

Claim 34

The method, as set forth in claim 28 , further comprising the step of converting the steering signal to a steering current.

Claim 35

The method, as set forth in claim 28 , further comprising the step of overriding the phase locked loop control signals with the steering signal.

Claim 36

A circuit for aiding proper frequency lock in a phase locked loop, comprising: a phase detector adapted for receiving an input signal and an oscillator output signal from the phase locked loop and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal, wherein the phase detector comprises: a first RS latch receiving the input signal at its set input; a second RS latch receiving the inverted output of the first RS latch at its reset input; a third RS latch receiving the oscillator output signal at its set input; a fourth RS latch receiving the inverted output of the first RS latch at its reset input; a NAND gate coupled to the non-inverted outputs of the second and fourth RS latches, and the inverted outputs of the first and third RS latches, and generating an output; the output from the NAND gate further being coupled to the set inputs of the second and fourth RS latches; a first AND gate being coupled to the inverted output of the first RS latch and the output of the NAND gate, the output of the first AND gate being coupled to the reset input of the first RS latch; a second AND gate being coupled to the inverted output of the third RS latch and the output of the NAND gate, the output of the second AND gate being coupled to the reset input of the third RS latch; and the up pulse width modulated cycle slip signal being the inverted output of the first RS latch, and the down pulse width modulated cycle slip signal being the inverted output of the third RS latch; a first latch adapted for latching the up pulse width modulated cycle slip signal with the input signal; a first logic circuit adapted for receiving the latched up pulse width modulated cycle slip signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal; a second latch adapted for latching the down pulse width modulated cycle slip signal with the oscillator output signal; a second logic circuit adapted for receiving the latched down pulse width modulated cycle slip signal and generating a down cycle slip signal- indicative that the oscillator output signal is ahead of the input signal; and a phase correction circuit generating a steering signal in response to the up and down cycle slip signals.

Claim 37

A circuit for aiding proper frequency lock in a phase locked loop, comprising: a phase detector adapted for receiving an input signal and an oscillator output signal from the phase locked loop and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal, wherein the phase detector comprises: a first RS latch receiving the input signal at its set input; a second RS latch receiving the inverted output of the first RS latch at its reset input; a third RS latch receiving the oscillator output signal at its set input; a fourth RS latch receiving the inverted output of the first RS latch at its reset input; a NAND gate coupled to the non-inverted outputs of the second and fourth RS latches, and the inverted outputs of the first and third RS latches, and generating an output; the output from the NAND gate further being coupled to the set inputs of the second and fourth RS latches; a first AND gate being coupled to the inverted output of the first RS latch and the output of the NAND gate, the output of the first AND gate being coupled to the reset input of the first RS latch; a second AND gate being coupled to the inverted output of the third RS latch and the output of the NAND gate, the output of the second AND gate being coupled to the reset input of the third RS latch; and the up pulse width modulated cycle slip signal being the inverted output of the first RS latch, and the down pulse width modulated cycle slip signal being the inverted output of the third RS latch; a first latch adapted for latching the up pulse width modulated cycle slip signal with the input signal; a first logic circuit adapted for receiving the latched up pulse width modulated cycle slip signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal; a second latch adapted for latching the down pulse width modulated cycle slip signal with the oscillator output signal; a second logic circuit adapted for receiving the latched down pulse width modulated cycle slip signal and generating a down cycle slip signal- indicative that the oscillator output signal is ahead of the input signal; and a phase correction circuit generating a steering signal in response to the up and down cycle slip signals.

Claim 38

The circuit, as set forth in claim 31 , wherein the phase correction circuit comprises: a cycle slip circuit receiving the up and down cycle slip signals and being adapted for generating a cycle slip signal in response to a predetermined number of consecutive up or down cycle slip signals being received; and a fixed up/down counter receiving the up and down cycle slip signals and being adapted for generating a steering signal indicative of the amount of correction desired.

Claim 39

The circuit, as set forth in claim 32 , wherein the phase correction circuit further comprises a digital to analog converter coupled to the fixed up/down counter being adapted for converting the steering signal into a steering current.

Claim 40

The circuit, as set forth in claim 32 , wherein the cycle slip circuit comprises a cycle slip counter for counting a predetermined number of consecutive up cycle slip signals or a predetermined number of consecutive down cycle slip signals being received.

Claim 41

The circuit, as set forth in claim 31 , wherein the phase correction circuit comprises a state machine.

Claim 42

The circuit, as set forth in claim 31 , wherein the up cycle slip detector comprises: a latch adapted for latching the up pulse width modulated cycle slip signal with the input signal; and a logic circuit adapted for receiving the latched up pulse width modulated cycle slip signal and generating an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal.

Claim 43

The circuit, as set forth in claim 31 , wherein the down cycle slip detector comprises: a latch adapted for latching the down pulse width modulated cycle slip signal with the oscillator output signal; and a logic circuit adapted for receiving the latched down pulse width modulated cycle slip signal and generating a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal.