Phase-locked loop circuit with a multi-cycle phase detector and multi-current charge pump

Claim 2

A phase-locked loop circuit for locking the phase of an oscillator output signal to the phase of a reference signal, comprising: a phase detector for detecting a phase difference between an input signal and said reference signal through multiple clock cycles, and for providing a first phase detector output signal representative of a detected phase difference less than a single cycle, and for providing a second phase detector output signal representative of a detected phase difference greater than a single cycle; control means, receiving said first phase detector output signal and said second phase detector output signal, for providing a voltage controlled oscillator (VCO) control signal controlled by said first phase detector output signal and said second phase detector output signal; a voltage controlled oscillator receiving said VCO control signal and providing said oscillator output signal which is applied to said phase detector as the input signal thereof.

Claim 3

A phase locked loop as in claim 1 wherein said control means comprises: a first control signal source, responsive to said first phase detector output signal, providing a first control signal representative of a phase difference between said reference signal and said input signal less than a single cycle; and a second control signal source, responsive to said second phase detector output signal, providing a second control signal representative of a phase difference between said reference signal and said input signal greater than a single cycle.

Claim 4

A phase locked loop as in claim 1 wherein said control means comprises: a charge pump responsive to said first and said second phase detector output signals and for providing a charge pump output signal; and a loop filter responsive to said charge pump output signal and providing a filtered output signal.

Claim 5

A phase locked loop as in claim 3 wherein said charge pump comprises: a first current source responsive to said first phase detector output signal for outputting a first current; and a second current source responsive to said second phase detector output signal for outputting a second current.

Claim 6

A phase locked loop circuit for locking the phase of an oscillator output signal to the phase of a reference signal, comprising; a phase detector for detecting a phase difference between an input signal and said reference signal through multiple clock cycles, and for providing a first phase detector output signal representative of a detected phase difference less than a single cycle, and for providing a second phase detector output signal representative of a detected phase difference greater than a single cycle; control means, receiving said first phase detector output signal and said second phase detector output signal, for providing a voltage controlled oscillator (VCO) control signal controlled by said first phase detector output signal and said second phase detector output signal, wherein said control means comprises: a first control signal source, responsive to said first phase detector output signal, providing a first control signal representative of a phase difference between said reference signal and said input signal less than a single cycle, and a second control signal source, responsive to said second phase detector output signal, providing a second control signal representative of a phase difference between said reference signal and said input signal greater than a single cycle, a charge pump responsive to said first and said second phase detector output signals and for providing a charge pump output signal said charge pump comprising a first current source responsive to said first phase detector output signal for outputting a first current, and a second current source responsive to said second phase detector output signal for outputting a second current, and a loop filter responsive to said charge pump output signal and providing a filtered output signal; and a voltage controlled oscillator receiving said VCO control signal and providing said oscillator output signal which is applied to said phase detector as the input signal thereof; and wherein said phase detector provides said first phase detector signal as duty cycle modulated pulses.

Claim 7

A phase locked loop circuit for locking the phase of an oscillator output signal to the phase of a reference signal, comprising; a phase detector for detecting a phase difference between an input signal and said reference signal through multiple clock cycles, and for providing a first phase detector output signal representative of a detected phase difference less than a single cycle, and for providing a second phase detector output signal representative of a detected phase difference greater than a single cycle; control means, receiving said first phase detector output signal and said second phase detector output signal, for providing a voltage controlled oscillator (VCO) control signal controlled by said first phase detector output signal and said second phase detector output signal, wherein said control means comprises: a first control signal source, responsive to said first phase detector output signal, providing a first control signal representative of a phase difference between said reference signal and said input signal less than a single cycle, and a second control signal source, responsive to said second phase detector output signal, providing a second control signal representative of a phase difference between said reference signal and said input signal greater than a single cycle, a charge pump responsive to said first and said second phase detector output signals and for providing a charge pump output signal said charge pump comprising a first current source responsive to said first phase detector output signal for outputting a first current, and a second current source responsive to said second phase detector output signal for outputting a second current, and a loop filter responsive to said charge pump output signal and providing a filtered output signal; and a voltage controlled oscillator receiving said VCO control signal and providing said oscillator output signal which is applied to said phase detector as the input signal thereof; and wherein said phase detector provides said first phase detector signal as duty cycle modulated pulses.

Claim 8

A phase locked loop as in claim 5 wherein: said phase detector further comprises a latch, settable upon detection of a slippage of a cycle and resettable upon detection of a slippage of a cycle in a opposite direction of slippage causing a set of said latch, and said second phase detector output signal is the output of said latch.

Claim 9

A phase locked loop as in claim 6 wherein: said phase detector further comprises means for cancelling digitally said second phase detector output signal during the time said first phase detector output signal is active.

Claim 10

A phase locked loop as in claim 6, wherein the first control signal and and the second control signal are provided each at a predermined level, active during the time the first phase detector output signal and the second phase detector output signal, respectively, are active.

Claim 11

A phase locked loop as in claim 8, wherein the predetermined level of said second control signal is substantially larger than the predetermined level of said first control signal.

Claim 12

A phase locked loop as in claim 6 wherein: said phase detector further comprises means for cancelling digitally said second phase detector signal during the time said first phase detector output signal is active; the first control signal and the second control signal are provided each at a predermined level, active during the time the first phase detector output signal and the second phase detector output signal, respectively, are active; and the predetermined level of said second control signal is substantially larger than the predetermined level of said first control signal.

Claim 13

A phase locked loop as in claim 8, wherein the predetermined level of said second control signal is substantially the same as the predetermined level of said first control signal.