Cycle slip detector and phase locked loop circuit and digital signal reproducing apparatus using the same

Claim 2

A cycle slip detector for detecting a cycle slip in a phase error signal, comprising: first determining means for determining that the value of said phase error signal being supplied thereto is larger than a first threshold value near a maximum value possibly taken by said phase error signal to generate a first determining signal; second determining means for determining that the value of said phase error signal being supplied thereto is smaller than a second threshold value near a minimum value possibly taken by said phase errors to generate a second determining signal; and detecting signal generating means for generating a cycle slip detecting signal when said first determining signal and said second determining signal are generated in succession.

Claim 3

A cycle slip detector according to claim 1, wherein said first and second threshold values are variable.

Claim 4

A phase locked loop circuit for generating a phase synchronizing signal synchronized in phase to an input signal, comprising: error detecting means for detecting a phase error in said input signal and for generating a phase error signal in accordance the detected phase error; a cycle slip detector including first determining means for determining that the value of said phase error signal being supplied thereto is larger than a first threshold value near a maximum value possibly taken by said phase error signal to generate a first determining signal; second determining means for determining that the value of said phase error signal being supplied thereto is smaller than a second threshold value near a minimum value possibly taken by said phase error signal to generate a second determining signal; and detecting signal generating means for generating a cycle slip detecting signal when said first determining signal and said second determining signal are generated in succession; an adding means for adding said phase error signal and said cycle slip detecting signal to generate a sum signal in accordance with an addition value of both said signals; a loop filter for passing a low frequency component of said sum signal therethrough; and oscillating means for generating said phase synchronizing signal having an oscillating frequency and a phase in accordance with said low frequency component.

Claim 5

A phase locked loop circuit for generating a phase synchronizing signal synchronized in phase to an input signal, comprising: error detecting means for detecting a phase error in said input signal and for generating a phase error signal in accordance the detected phase error; a cycle slip detector including first determining means for determining that the value of said phase error signal being supplied thereto is larger than a first threshold value near a maximum value possibly taken by said phase error signal to generate a first determining signal; second determining means for determining that the value of said phase error signal being supplied thereto is smaller than a second threshold value near a minimum value possibly taken by said phase error signal to generate a second determining signal; and detecting signal generating means for generating a cycle slip detecting signal when said first determining signal and said second determining signal are generated in succession; an adding means for adding said phase error signal and said cycle slip detecting signal to generate a sum signal in accordance with an addition value of both said signals; a loop filter for passing a low frequency component of said sum signal therethrough; and oscillating means for generating said phase synchronizing signal having an oscillating frequency and a phase in accordance with said low frequency component.

Claim 6

A phase locked loop circuit according to claim 3, further comprising digitizing means for converting said input signal to a digital signal using a sampling timing signal to output the digital signal, wherein said error detecting means detects a phase error in sampling timing of the digitizing means relative to said input signal, and generates said phase error signal in response to the detection of the phase error.

Claim 7

A phase locked loop circuit according to claim 3, further comprising: pull-in state detecting means for detecting that the oscillating frequency of said oscillating means is within a phase pull-in possible frequency range to generate a pull-in state detecting signal; and threshold value setting means for changing said first and second threshold values in response to said pull-in state detecting signal.

Claim 8

A phase locked loop circuit according to claim 5, wherein said threshold value setting means makes the difference between said first threshold value and said second threshold value during a period in which said pull-in state detecting signal is generated larger than the difference between said first threshold value and said second threshold value during a period in which said pull-in state detecting signal is not generated.

Claim 9

A phase locked loop circuit according to claim 3, further comprising an input signal evaluating means for detecting an average amplitude value or a peak value of said input signal, wherein said threshold setting means changes said first and second threshold values in response to said average amplitude value or said peak value.

Claim 10

A phase locked loop circuit according to claim 3, wherein said cycle slip detecting signal is a pulse signal, and said phase locked loop circuit further comprising means for making the pulse width of said cycle slip detecting signal variable.

Claim 11

A phase locked loop circuit according to claim 3, wherein said detecting signal generating means generates a cycle slip detecting signal having a first level when said second determining signal is generated subsequent to the generation of said first determining signal, and generates a cycle slip detecting signal having a second level with a polarity reverse to said first level relative to a reference level when said first determining signal is generated subsequent to the generation of said second determining signal.

Claim 12

A digital signal reproducing apparatus for reproducing a digital signal from a read signal acquired by reading a recording medium, comprising: digitizing means for converting said reading signal to a digital form using a sampling timing signal and for outputting a digital signal; error detecting means for detecting a phase error in sampling timing of said digitizing means relative to said read signal to generate a phase error signal in accordance with said phase error; a cycle slip detector including first determining means for determining that the value of said phase error signal being supplied thereto is larger than a first threshold value near a maximum value possibly taken by said phase error signal to generate a first determining signal; second determining means for determining that the value of said phase error signal being supplied thereto is smaller than a second threshold value near a minimum value possibly taken by said phase error signal to generate a second determining signal; and detecting signal generating means for generating a cycle slip detecting signal when said first determining signal and said second determining signal are generated in succession; adding means for adding said phase error signal and said cycle slip detecting signal to generate a sum signal in accordance with an addition value of both said signals; a loop filter for passing a low frequency component of said sum signal therethrough; oscillating means for generating said sampling timing signal having an oscillating frequency and a phase in accordance with said low frequency component; and decoding means for decoding said digital signal.

Claim 13

A digital signal reproducing apparatus for reproducing a digital signal from a read signal acquired by reading a recording medium, comprising: digitizing means for converting said reading signal to a digital form using a sampling timing signal and for outputting a digital signal; error detecting means for detecting a phase error in sampling timing of said digitizing means relative to said read signal to generate a phase error signal in accordance with said phase error; a cycle slip detector including first determining means for determining that the value of said phase error signal being supplied thereto is larger than a first threshold value near a maximum value possibly taken by said phase error signal to generate a first determining signal; second determining means for determining that the value of said phase error signal being supplied thereto is smaller than a second threshold value near a minimum value possibly taken by said phase error signal to generate a second determining signal; and detecting signal generating means for generating a cycle slip detecting signal when said first determining signal and said second determining signal are generated in succession; adding means for adding said phase error signal and said cycle slip detecting signal to generate a sum signal in accordance with an addition value of both said signals; a loop filter for passing a low frequency component of said sum signal therethrough; oscillating means for generating said sampling timing signal having an oscillating frequency and a phase in accordance with said low frequency component; and decoding means for decoding said digital signal.