US6404240B1
Expired / Lapsed
US
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Circuit and method of a three state phase frequency lock detector
Assignee: Semiconductor Components Industries LLC
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Filing: 2000-10-30
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Granted: 2002-06-11
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Expires: 2020-10-30
Abstract
Abstract A three state phase frequency lock detector ( 14 ) is provided which monitors the UP and DOWN phase pulses generated by a three state phase frequency detector (PFD). The lock detector ( 14 ) asserts the lock detect signal when the rising edges of the UP and DOWN phase pulses are phase aligned and un-asserts the lock detect signal for all other relative phases of the UP and DOWN phase pulses. Lock detector ( 14 ) is capable of reporting the lock detect signal for each cycle of the UP and DOWN pulses.
Inventors
- 👤 Harsha Sharath Hakkal
- 👤 Joseph Jason Hughes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:11
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03D; H03D13/00; H03D13/003; H03D13/004; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03L7/0895; H03L7/0898; H03L7/095; H03L7/10; H03L7/107; H03L7/1072; H03L7/1075
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
97 words
A three state phase frequency lock detection circuit, comprising; a phase detector; a first memory storage device coupled to a first output of the phase detector for receiving a first signal indicative of a first phase; a second memory storage device coupled to a second output of the phase detector for receiving a second signal indicative of a second phase; and a logic circuit coupled to receive an output of the first and second memory storage devices and coupled to provide a logic signal indicating that the phase of the first and second signals are substantially equivalent.
Claim 2
Dependent Claim
97 words
A three state phase frequency lock detection circuit, comprising; a phase detector; a first memory storage device coupled to a first output of the phase detector for receiving a first signal indicative of a first phase; a second memory storage device coupled to a second output of the phase detector for receiving a second signal indicative of a second phase; and a logic circuit coupled to receive an output of the first and second memory storage devices and coupled to provide a logic signal indicating that the phase of the first and second signals are substantially equivalent.
Claim 3
Dependent Claim
64 words
The three state phase frequency lock detection circuit of claim 1 wherein the first memory storage device includes a positive edge triggered D-type flip flop having a first input coupled to receive the first signal, a second input coupled to receive the second signal and having an output coupled to provide a third signal representative of the first signal enabled by the second signal.
Claim 4
Dependent Claim
64 words
The three state phase frequency lock detection circuit of claim 1 wherein the second memory storage device includes a positive edge triggered D-type flip flop having a first input coupled to receive the second signal, a second input coupled to receive the first signal and having an output coupled to provide a fourth signal representative of the second signal enabled by the first signal.
Claim 5
Dependent Claim
39 words
The three state phase frequency lock detection circuit of claim 1 wherein the logic circuit includes an AND gate having a first input coupled to receive the third signal and a second input coupled to receive the fourth signal.
Claim 6
Dependent Claim
132 words
A lock detect circuit providing a phase alignment status indication between a first data signal and a second data signal, comprising: a phase detector having first and second inputs for receiving the first and second data signals; a first memory storage device having a first input coupled to a first output of the phase detector and a second input coupled to a second output of the phase detector; a second memory storage device having a first input coupled to the second output of the phase detector and a second input coupled to the first output of the phase detector; and a logic circuit coupled to received the outputs of the first and second memory storage devices and having an output coupled to provide a logic signal indicative of the phase alignment status.
Claim 7
Dependent Claim
132 words
A lock detect circuit providing a phase alignment status indication between a first data signal and a second data signal, comprising: a phase detector having first and second inputs for receiving the first and second data signals; a first memory storage device having a first input coupled to a first output of the phase detector and a second input coupled to a second output of the phase detector; a second memory storage device having a first input coupled to the second output of the phase detector and a second input coupled to the first output of the phase detector; and a logic circuit coupled to received the outputs of the first and second memory storage devices and having an output coupled to provide a logic signal indicative of the phase alignment status.
Claim 8
Dependent Claim
41 words
The lock detect circuit of claim 5 wherein the first memory storage device includes a positive edge triggered D-type flip flop having an output coupled to provide an output signal representing the first data signal enabled by the first clock signal.
Claim 9
Dependent Claim
41 words
The lock detect circuit of claim 5 wherein the second memory storage device includes a positive edge triggered D-type flip flop having an output coupled to provide an output signal representing the second data signal enabled by the second clock signal.
Claim 10
Dependent Claim
15 words
The lock detect circuit of claim 5 wherein the logic circuit includes an AND gate.
Claim 11
Dependent Claim
197 words
A three state phase frequency lock detection circuit, comprising: a first memory storage circuit having a first input coupled to receive a first phase detector signal and a second input coupled to receive a second phase detector signal; wherein the first memory storage circuit further comprises a buffer having an input coupled to receive the first data signal, and a memory storage device having a first input coupled to receive the second data signal and a second input coupled to receive an output of the buffer; a second memory storage circuit having a first input coupled to receive the second phase detector signal and a second input coupled to receive the first phase detector signal; wherein the second memory storage circuit further comprises a buffer having an input coupled to receive the second data signal, and a memory storage device having a first input coupled to receive the first data signal and a second input coupled to receive an output of the buffer; and a logic circuit having a first input coupled to receive an output of the first memory storage circuit and a second input coupled to receive an output of the second memory storage circuit.
Claim 12
Dependent Claim
197 words
A three state phase frequency lock detection circuit, comprising: a first memory storage circuit having a first input coupled to receive a first phase detector signal and a second input coupled to receive a second phase detector signal; wherein the first memory storage circuit further comprises a buffer having an input coupled to receive the first data signal, and a memory storage device having a first input coupled to receive the second data signal and a second input coupled to receive an output of the buffer; a second memory storage circuit having a first input coupled to receive the second phase detector signal and a second input coupled to receive the first phase detector signal; wherein the second memory storage circuit further comprises a buffer having an input coupled to receive the second data signal, and a memory storage device having a first input coupled to receive the first data signal and a second input coupled to receive an output of the buffer; and a logic circuit having a first input coupled to receive an output of the first memory storage circuit and a second input coupled to receive an output of the second memory storage circuit.
Claim 13
Dependent Claim
20 words
The lock detect circuit of claim 9 wherein the memory storage device includes a positive edge triggered D-type flip flop.
Claim 14
Dependent Claim
20 words
The lock detect circuit of claim 9 wherein the memory storage device includes a positive edge triggered D-type flip flop.
Claim 15
Independent Claim
92 words
A method of operating a three state phase frequency lock detection circuit, comprising: comparing first and second signals to produce firstand second phase detected signals; storing the first phase detected signal on a transition of the second phase detected signal as a first stored signal; storing the second phase detected signal on a transition of the first phase detected signal as a second stored signal; and comparing the first and second stored signals to provide a lock detection signal when the first and second signals are substantially operating at the same phase.
Claim 16
Independent Claim
92 words
A method of operating a three state phase frequency lock detection circuit, comprising: comparing first and second signals to produce firstand second phase detected signals; storing the first phase detected signal on a transition of the second phase detected signal as a first stored signal; storing the second phase detected signal on a transition of the first phase detected signal as a second stored signal; and comparing the first and second stored signals to provide a lock detection signal when the first and second signals are substantially operating at the same phase.
Claim 17
Dependent Claim
68 words
The method of claim 12 wherein comparing the phase difference between the first and second signals includes: providing the first signal to a first memory storage device; providing the second signal to a second memory storage device; extracting the first signal from the first memory storage device enabled by the second signal; and extracting the second signal from the second memory storage device enabled by the first signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-06-10 | 2005-12-10 | 2006-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-06-10 | 2009-12-10 | 2010-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-06-10 | 2013-12-10 | 2014-06-11 | $7700.00 | Window Closed / Lapsed |