US5159279A
Expired / Lapsed
US
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Apparatus and method for detecting out-of-lock condition in a phase lock loop
Assignee: Xylon LLC
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Filing: 1990-11-27
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Granted: 1992-10-27
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Expires: 2010-11-27
Abstract
Abstract A circuit is provided for detecting out-of-lock condition in a phase lock loop. The phase lock loop receives a first signal having a first frequency and a voltage controlled oscillator of the phase lock loop produces a second signal having a second frequency. The circuit comprises a first data flip-flop coupled to the phase lock loop for receiving the first signal and clocked by the second signal. The first flip-flop produces an inverted output of the first signal. A second flip-flop is coupled to the phase lock loop for receiving the second signal clocked by the first signal, and produces a non-inverted output of the second signal. Additionally, an EXCLUSIVE-OR gate is coupled to the first and second flip-flops for receiving the inverted and non-inverted output thereof and producing a signal indicative of an out-of-lock condition.
Inventors
- 👤 Kishan Shenoi
- 👤 David J. Wetle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:46
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/26; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/095
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
121 words
A circuit for detecting out-of-lock condition in a phase lock loop, said phase lock loop receiving a first signal having a first frequency and including a voltage controlled oscillator, said voltage controlled oscillator producing a second signal having a second frequency, said circuit comprising: a first flip-flop coupled to said phase lock loop for receiving said first signal clocked by said second signal, and producing an inverted output of said first signal; a second flip-flop coupled to said phase lock loop for receiving said second signal clocked by said first signal, and producing a non-inverted output of said second signal; and a logic circuit for receiving said inverted and non-inverted output and producing an out-of-lock signal indicative of an out-of-lock condition.
Claim 2
Dependent Claim
121 words
A circuit for detecting out-of-lock condition in a phase lock loop, said phase lock loop receiving a first signal having a first frequency and including a voltage controlled oscillator, said voltage controlled oscillator producing a second signal having a second frequency, said circuit comprising: a first flip-flop coupled to said phase lock loop for receiving said first signal clocked by said second signal, and producing an inverted output of said first signal; a second flip-flop coupled to said phase lock loop for receiving said second signal clocked by said first signal, and producing a non-inverted output of said second signal; and a logic circuit for receiving said inverted and non-inverted output and producing an out-of-lock signal indicative of an out-of-lock condition.
Claim 3
Dependent Claim
39 words
The circuit, as set forth in claim 1, further comprising a counter coupled to said logic circuit for receiving said out-of-lock signal at a clocking input, and producing a count of the number of occurrences of said out-of-lock signal.
Claim 4
Dependent Claim
28 words
The circuit, as set forth in claim 2, further comprising a microprocessor coupled to said counter for receiving said count of the number of said out-of-lock signal occurrences.
Claim 5
Dependent Claim
20 words
The circuit, as set forth in claim 3, wherein said microprocessor further produces a clear signal for resetting said counter.
Claim 6
Dependent Claim
50 words
The circuit, as set forth in claim 1, wherein said first and second signals have rising and falling edges, said first flip-flop receives said first signal at the rising edge of said second signal, and said second flip-flop receives said second signal at the rising edge of said first signal.
Claim 7
Dependent Claim
50 words
The circuit, as set forth in claim 1, wherein said first and second signals have rising and falling edges, said first flip-flop receives said first signal at the falling edge of said second signal, and said second flip-flop receives said second signal at the falling edge of said first signal.
Claim 8
Dependent Claim
19 words
The circuit, as set forth in claim 1, wherein said first and second flip-flops are edge sensitive data flip-flops.
Claim 9
Dependent Claim
16 words
The circuit, as set forth in claim 1, wherein said logic circuit performs an exclusive-OR function.
Claim 10
Dependent Claim
16 words
The circuit, as set forth in claim 1, wherein said logic circuit is an exclusive-OR gate.
Claim 11
Dependent Claim
129 words
A circuit for detecting out-of-lock condition in a phase lock loop, said phase lock loop receiving a first signal having a first frequency and including a voltage controlled oscillator, said voltage controlled oscillator producing a second signal having a second frequency, said circuit comprising: first means coupled to said phase lock loop for receiving said first signal clocked by said second signal and producing an inverted output of said first signal; second means coupled to said phase lock loop for receiving said second signal clocked by said first signal, and producing a non-inverted output of said second signal; and logic means for receiving said inverted and non-inverted outputs and producing an out-of-lock signal indicative of an out-of-lock condition whenever only one of said inverted and non-inverted outputs is high.
Claim 12
Dependent Claim
129 words
A circuit for detecting out-of-lock condition in a phase lock loop, said phase lock loop receiving a first signal having a first frequency and including a voltage controlled oscillator, said voltage controlled oscillator producing a second signal having a second frequency, said circuit comprising: first means coupled to said phase lock loop for receiving said first signal clocked by said second signal and producing an inverted output of said first signal; second means coupled to said phase lock loop for receiving said second signal clocked by said first signal, and producing a non-inverted output of said second signal; and logic means for receiving said inverted and non-inverted outputs and producing an out-of-lock signal indicative of an out-of-lock condition whenever only one of said inverted and non-inverted outputs is high.
Claim 13
Dependent Claim
39 words
The circuit, as set forth in claim 10, further comprising counting means coupled to said logic means for receiving said out-of-lock signal at a clocking input, and producing a count of the number of occurrence of said out-of-lock signal.
Claim 14
Dependent Claim
29 words
The circuit, as set forth in claim 11, further comprising processing means coupled to said counting means for receiving said count of said the number of out-of-lock signal occurrences.
Claim 15
Dependent Claim
22 words
The circuit, as set forth in claim 12, wherein said processing means further produces a clear signal for resetting said counting means.
Claim 16
Dependent Claim
50 words
The circuit, as set forth in claim 10, wherein said first and second signals have rising and falling edges, said first means receives said first signal at the rising edge of said second signal, and said second means receives said second signal at the rising edge of said first signal.
Claim 17
Dependent Claim
50 words
The circuit, as set forth in claim 10, wherein said first and second signals have rising and falling edges, said first means receives said first signal at the falling edge of said second signal, and said second means receives said second signal at the falling edge of said first signal.
Claim 18
Dependent Claim
17 words
The circuit, as set forth in claim 10, wherein said first and second means are data flip-flops.
Claim 19
Dependent Claim
16 words
The circuit, as set forth in claim 10, wherein said logic circuit is an exclusive-OR gate.
References Cited (Backward Citations)
US4267514A
Cited
US4385395A
Cited
US4422176A
Cited
US4400667A
Cited
US4535459A
Cited
US4574243A
Cited
US4668917A
Cited
US4775840A
Cited
US4988901A
Cited
US5027085A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-27 | 1996-04-27 | 1996-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-27 | 2000-04-27 | 2000-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-27 | 2004-04-27 | 2004-10-27 | $7700.00 | Window Closed / Lapsed |