Circuit indicating the phase relation between several signals having the same frequency

Claim 2

A circuit for indicating a first or a last signal activated among a plurality of signals, comprising: a plurality of flip-flops respectively associated with a plurality of pairs of the plurality of signals, a first signal of each pair being applied to a reset input of a flip-flop and a second signal of each pair being applied to a set input of the flip-flop; and a plurality of logic gates, each logic gate being respectively associated with one of the plurality of signals, and connected to outputs of a group of flip-flops of the plurality of the flip-flops, each flip-flop of the group of flip-flops receiving the one of the plurality of signals respectively associated with the logic gate, as one of a first signal and a second signal of a pair respectively associated with the flip-flop, an output signal provided by each of the plurality of logic gates indicating whether the respectively associated one of the plurality of signals is the first or the last activated signal relative to all of the plurality of signals.

Claim 3

The indication circuit of claim 1, wherein the plurality of flip-flops includes a flip-flop for each pair of signals, the pairs being formed so that two distinct signals occur only once in a pair, and wherein the output signal provided by each logic gate indicates that the respectively associated one of the plurality of signals is the first or the last activated signal relative to all of the plurality of signals when the flip-flops of the group of flip-flops having outputs connected to the logic gate are in a particular state.

Claim 4

The indication circuit of claim 1, wherein the signals are periodic signals having a same frequency, the circuit further comprising: a register coupled to outputs of the plurality of logic gates, and enabled when each of the plurality of signals is in an active state.

Claim 5

An adjustment circuit for adjusting the skew between several clock signals that have a same frequency and are respectively provided by a plurality of delay devices, wherein an output impedance of each delay device is independently adjustable, said adjustment circuit including: an indication circuit that indicates the clock signal having a maximum phase lag; and control means for controlling output impedances of the plurality of delay devices, wherein the control means controls an increase of the output impedance of the respective delay device that provides the clock signal having the maximum phase lag independently from controlling other delay devices of the plurality of delay devices, wherein said control means includes means for incrementing an impedance of a particular delay device associated with a particular clock signal in phase advance of the clock signal having the maximum phase lag until an output signal of a flip-flop of the indication circuit indicates that the particular clock signal is no longer in phase advance, and wherein each delay device includes a plurality of inverters that may be individually connected in parallel with a first inverter, depending on the state of a register whose content is modified by successive pulses provided by the control means.

Claim 6

An adjustment circuit for adjusting the skew between several clock signals that have a same frequency and are respectively provided by a plurality of delay devices, wherein an output impedance of each delay device is independently adjustable, said adjustment circuit including: an indication circuit that indicates the clock signal having a maximum phase lag; and control means for controlling output impedances of the plurality of delay devices, wherein the control means controls an increase of the output impedance of the respective delay device that provides the clock signal having the maximum phase lag independently from controlling other delay devices of the plurality of delay devices, wherein said control means includes means for incrementing an impedance of a particular delay device associated with a particular clock signal in phase advance of the clock signal having the maximum phase lag until an output signal of a flip-flop of the indication circuit indicates that the particular clock signal is no longer in phase advance, and wherein each delay device includes a plurality of inverters that may be individually connected in parallel with a first inverter, depending on the state of a register whose content is modified by successive pulses provided by the control means.

Claim 7

A circuit for adjusting a phase relation between a plurality of signals, the circuit comprising: means for outputting the plurality of signals; means for receiving and comparing the outputted plurality of signals, and outputting a result indicating a phase relation between the outputted plurality of signals, wherein the means for receiving and comparing, and outputting includes means for identifying a particular signal of the outputted plurality of signals having a maximum phase lag; and means for receiving the outputted result, and adjusting the means for outputting the plurality of signals to modify a skew between two signals according to the outputted result the phase relation being adjusted when the skew is modified.

Claim 8

A circuit for adjusting a phase relation between a plurality of signals, the circuit comprising: means for outputting the plurality of signals; means for receiving and comparing the outputted plurality of signals, and outputting a result indicating a phase relation between the outputted plurality of signals, wherein the means for receiving and comparing, and outputting includes means for identifying a particular signal of the outputted plurality of signals having a maximum phase lag; and means for receiving the outputted result, and adjusting the means for outputting the plurality of signals to modify a skew between two signals according to the outputted result the phase relation being adjusted when the skew is modified.

Claim 9

The circuit of claim 5, wherein the means for receiving and comparing, and outputting further includes means for generating the result according to the identified particular signal.

Claim 10

The circuit of claim 6, wherein the result includes each signal of the plurality of signals except the identified particular signal, and a substitute signal that replaces the identified particular signal.

Claim 11

A circuit for adjusting a phase relation between a plurality of signals, the circuit comprising: means for outputting the plurality of signals; means for receiving and comparing the outputted plurality of signals, and outputting a result indicating a phase relation between the outputted plurality of signals; and means for receiving the outputted result, and adjusting the means for outputting the plurality of signals to modify a skew between two signals according to the outputted result, the phase relation being adjusted when the skew is modified, wherein the means for receiving and adjusting includes means for selecting a set of signals of the plurality of signals to be delayed according to the received result.

Claim 12

A circuit for adjusting a phase relation between a plurality of signals, the circuit comprising: means for outputting the plurality of signals; means for receiving and comparing the outputted plurality of signals, and outputting a result indicating a phase relation between the outputted plurality of signals; and means for receiving the outputted result, and adjusting the means for outputting the plurality of signals to modify a skew between two signals according to the outputted result, the phase relation being adjusted when the skew is modified, wherein the means for receiving and adjusting includes means for selecting a set of signals of the plurality of signals to be delayed according to the received result.

Claim 13

The circuit of claim 8, wherein the means for outputting the plurality of signals includes means for delaying the plurality of signals according to the set of signals selected by the means for selecting.

Claim 14

The circuit of claim 9, wherein the means for delaying includes means for increasing a corresponding output impedance for each signal, a signal being delayed when the corresponding output impedance is increased.

Claim 15

The circuit of claim 10, wherein the means for increasing a corresponding output impedance for each signal includes means for switchably configuring a number of discrete impedance sources to increase the output impedance.

Claim 16

A circuit for adjusting a phase relation between a plurality of signals, the circuit comprising: a signal output stage that outputs the plurality of signals; a comparison circuit that receives and compares the outputted plurality of signals, and outputs a result indicating a phase relation between the outputted plurality of signals, wherein the comparison circuit includes an identification circuit that identifies a particular signal of the outputted plurality of signals having a maximum phase lag; and a control circuit that receives the outputted result and adjusts the signal output stage to modify a skew between two signals according to the outputted result, the phase relation between adjusted when the skew is modified.

Claim 17

A circuit for adjusting a phase relation between a plurality of signals, the circuit comprising: a signal output stage that outputs the plurality of signals; a comparison circuit that receives and compares the outputted plurality of signals, and outputs a result indicating a phase relation between the outputted plurality of signals, wherein the comparison circuit includes an identification circuit that identifies a particular signal of the outputted plurality of signals having a maximum phase lag; and a control circuit that receives the outputted result and adjusts the signal output stage to modify a skew between two signals according to the outputted result, the phase relation between adjusted when the skew is modified.

Claim 18

The circuit of claim 12, wherein the comparison circuit further includes a generation circuit that generates the result according to the identified particular signal.

Claim 19

The circuit of claim 13, wherein the result includes each signal of the plurality of signals except the identified particular signal, and a substitute signal that replaces the identified particular signal.

Claim 20

A circuit for adjusting a phase relation between a plurality of signals, the circuit comprising: a signal output stage that outputs the plurality of signals; a comparison circuit that receives and compares the outputted plurality of signals, and outputs a result indicating a phase relation between the outputted plurality of signals; and a control circuit that receives the outputted result and adjusts the signal output stage to modify a skew between two signals according to the outputted result, the phase relation between adjusted when the skew is modified, wherein the control circuit includes logic circuitry that outputs a set of delaying pulses to the signal output stage according to the received result.

Claim 21

A circuit for adjusting a phase relation between a plurality of signals, the circuit comprising: a signal output stage that outputs the plurality of signals; a comparison circuit that receives and compares the outputted plurality of signals, and outputs a result indicating a phase relation between the outputted plurality of signals; and a control circuit that receives the outputted result and adjusts the signal output stage to modify a skew between two signals according to the outputted result, the phase relation between adjusted when the skew is modified, wherein the control circuit includes logic circuitry that outputs a set of delaying pulses to the signal output stage according to the received result.

Claim 22

The circuit of claim 15, wherein the signal output stage includes a plurality of amplifiers that receive the set of delaying pulses from the controlling stage.

Claim 23

The circuit of claim 16, wherein each amplifier of the plurality of amplifiers has an adjustable output impedance, each amplifier increasing the adjustable output impedance of the amplifier upon receipt of a delaying pulse from the controlling stage, a signal being delayed when the corresponding output impedance is increased.

Claim 24

The circuit of claim 17, wherein each amplifier further includes an impedance circuit that switchably configures a plurality of inverters to increase the output impedance.

Claim 27

The method of claim 19, wherein step (B) further includes the step of generating the result according to the identified particular signal.

Claim 28

The method of claim 20, wherein the step of generating the result includes the step of providing each signal of the plurality of signals with the identified particular signal being replaced with a substitute signal.

Claim 29

A circuit for adjusting the phase relation between a plurality of signals, the method comprising the steps of: (A) outputting the plurality of signals; (B) receiving and comparing the outputted plurality of signals, and outputting a result indicating a phase relation between the outputted plurality of signals; and (C) receiving the result, and adjusting a skew between two signals according to the outputted result, the phase relation being adjusted when the skew is modified, wherein the step of receiving and adjusting includes the step of selecting a set of signals of the plurality of signals to be delayed according to the received result.

Claim 30

A circuit for adjusting the phase relation between a plurality of signals, the method comprising the steps of: (A) outputting the plurality of signals; (B) receiving and comparing the outputted plurality of signals, and outputting a result indicating a phase relation between the outputted plurality of signals; and (C) receiving the result, and adjusting a skew between two signals according to the outputted result, the phase relation being adjusted when the skew is modified, wherein the step of receiving and adjusting includes the step of selecting a set of signals of the plurality of signals to be delayed according to the received result.

Claim 31

The method of claim 22, wherein step (A) includes the step of delaying the plurality of signals according to the set of signals selected in step (C).

Claim 32

The method of claim 23, wherein the step of delaying includes the step of increasing the corresponding output impedance for each signal, a signal being delayed when the corresponding output impedance is increased.

Claim 33

The method of claim 24, wherein the step of increasing the corresponding output impedance for each signal includes the step of switchably configuring a number of discrete impedance sources to increase the output impedance.

Claim 34

A circuit for indicating a phase relation between a plurality of signals, wherein each signal has an activation edge, the circuit comprising: means for comparing a plurality of pairs of signals of the plurality of signals, and outputting a plurality of comparison results, comparison result being outputted for each compared pair of signals, wherein the means for comparing includes a plurality of means for receiving a first signal and a second signal of one of the pair of signals, and outputting one of the comparison results indicating an order of receipt of the activation edges of the first signal and the second signal; and means for receiving the plurality of comparison results, and outputting an identification result identifying a particular signal of the plurality of signals as having one of a maximum phase lag and a maximum phase advance relative to the other signals of the plurality of signals according to the comparison results, wherein the means for receiving the plurality of comparison results and outputting an identification result includes means for receiving the plurality of signals, and outputting the identification result when the activation edges of each signal are received.

Claim 35

A circuit for indicating a phase relation between a plurality of signals, wherein each signal has an activation edge, the circuit comprising: means for comparing a plurality of pairs of signals of the plurality of signals, and outputting a plurality of comparison results, comparison result being outputted for each compared pair of signals, wherein the means for comparing includes a plurality of means for receiving a first signal and a second signal of one of the pair of signals, and outputting one of the comparison results indicating an order of receipt of the activation edges of the first signal and the second signal; and means for receiving the plurality of comparison results, and outputting an identification result identifying a particular signal of the plurality of signals as having one of a maximum phase lag and a maximum phase advance relative to the other signals of the plurality of signals according to the comparison results, wherein the means for receiving the plurality of comparison results and outputting an identification result includes means for receiving the plurality of signals, and outputting the identification result when the activation edges of each signal are received.

Claim 36

A circuit for indicating a phase relation between a plurality of signals, wherein each signal has an activation edge, the circuit comprising: a plurality of flip-flops that compare a plurality of pairs of signals of the plurality of signals, and outputs a plurality of comparison results, a comparison result being outputted for each compared pair of signals, wherein each flip-flop includes a set input that receives a first signal and a reset input that receives a second signal of one of the pair of signals, and an output that outputs one of the comparison results indicating an order of receipt of the activation edges of the first signal and the second signal; and logic circuitry that receives the plurality of comparison results, and outputs an identification result identifying a particular signal of the plurality of signals as having one of a maximum phase lag and an maximum phase advance relative to the other signals of the plurality of signals according to the comparison results.

Claim 37

A circuit for indicating a phase relation between a plurality of signals, wherein each signal has an activation edge, the circuit comprising: a plurality of flip-flops that compare a plurality of pairs of signals of the plurality of signals, and outputs a plurality of comparison results, a comparison result being outputted for each compared pair of signals, wherein each flip-flop includes a set input that receives a first signal and a reset input that receives a second signal of one of the pair of signals, and an output that outputs one of the comparison results indicating an order of receipt of the activation edges of the first signal and the second signal; and logic circuitry that receives the plurality of comparison results, and outputs an identification result identifying a particular signal of the plurality of signals as having one of a maximum phase lag and an maximum phase advance relative to the other signals of the plurality of signals according to the comparison results.

Claim 38

The circuit of claim 27, wherein the logic circuitry includes an enabling stage that receives the plurality of signals, and outputs the identification result when the activation edges of each signal are received.