Patent US6807658B2 successfully refreshed from Google Patents.
US6807658B2
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Systems and methods for performing clock gating checks
Assignee: Broadcom International Pte Ltd
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Filing: 2002-06-05
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Granted: 2004-10-19
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Expires: 2022-06-05
Abstract
Abstract A gating signal checker system and method are provided to perform clock gating check on a logic cell. In accordance with one aspect of the invention, the system includes logic that determines a clock transition time of a clock input into the logic cell, and logic that determines a transition time of at least one gating signal input into the logic cell. Also included in the gating signal checker system is logic that calculates a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell, and logic that determines that the logic cell fails the clock gating check if the clock difference time is negative. In accordance with another aspect of the invention, a method performs a clock gating check on a logic cell by determining a clock transition time of a clock input into the logic cell, and determining a transition time of at least one gating signal input into the logic cell. Then, the method calculates a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell, and determines that the logic cell passes the clock gating check if the clock difference time is positive.
Inventors
- 👤 David James Mielke
- 👤 Gayvin E Stong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 02:42
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
117 words
A method for performing a clock gating check on a logic cell comprising the steps of: determining a clock transition time of a clock signal input into the logic cell; determining a transition time of at least one gating signal input into the logic cell; calculating a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell; determining that the logic cell passes the clock gating check if the clock difference time is not negative; subtracting approximately one-half of a clock transition period from the clock difference time; and subtracting approximately one-half of a gating signal transition period from the clock difference time.
Claim 2
Independent Claim
117 words
A method for performing a clock gating check on a logic cell comprising the steps of: determining a clock transition time of a clock signal input into the logic cell; determining a transition time of at least one gating signal input into the logic cell; calculating a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell; determining that the logic cell passes the clock gating check if the clock difference time is not negative; subtracting approximately one-half of a clock transition period from the clock difference time; and subtracting approximately one-half of a gating signal transition period from the clock difference time.
Claim 3
Dependent Claim
20 words
The method as defined in claim 1 , further comprising: subtracting a minimum buffer period from the clock difference time.
Claim 4
Dependent Claim
21 words
The method as defined in claim 1 , further comprising: subtracting a maximum overlap time period from the clock difference time.
Claim 5
Dependent Claim
21 words
The method as defined in claim 1 , further comprising: subtracting a reserve buffer time period from the clock difference time.
Claim 6
Independent Claim
127 words
A system for perfonning a clock gating check on a logic cell comprising: means for determining a clock transition time of a clock signal input into the logic cell; means for determining a transition time of at least one gating signal input into the logic cell; means for calculating a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell; and means for determining that the logic cell passes the clock gating check if the clock difference time is not negative; means for subtracting approximately half of a clock transition period from the clock difference time; and means for subtracting approximately half of a gating signal transition period from the clock difference time.
Claim 7
Independent Claim
127 words
A system for perfonning a clock gating check on a logic cell comprising: means for determining a clock transition time of a clock signal input into the logic cell; means for determining a transition time of at least one gating signal input into the logic cell; means for calculating a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell; and means for determining that the logic cell passes the clock gating check if the clock difference time is not negative; means for subtracting approximately half of a clock transition period from the clock difference time; and means for subtracting approximately half of a gating signal transition period from the clock difference time.
Claim 8
Dependent Claim
20 words
The system of claim 5 , further comprising: means for subtracting a minimum buffer period from the clock difference time.
Claim 9
Dependent Claim
21 words
The system of claim 5 , further comprising: means for subtracting a maximum overlap time period from the clock difference time.
Claim 10
Dependent Claim
21 words
The system of claim 5 , further comprising: means for subtracting a reserve buffer time period from the clock difference time.
Claim 11
Dependent Claim
153 words
A computer readable storage medium containing program code for performing a clock gating check on a logic cell comprising: a first code segment configured to determine a clock transition time of a clock signal input into the logic cell; a second code segment configured to determine a transition time of at least one gating signal input into the logic cell; a third code segment configured to calculate a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell; and a fourth code segment configured to determine that the logic cell fails the clock gating check if the clock difference time is negative; wherein said third code segment is further configured to: subtract approximately half of a clock transition period from the clock difference time; and subtract approximately half of a gating signal transition period from the clock difference time.
Claim 12
Dependent Claim
153 words
A computer readable storage medium containing program code for performing a clock gating check on a logic cell comprising: a first code segment configured to determine a clock transition time of a clock signal input into the logic cell; a second code segment configured to determine a transition time of at least one gating signal input into the logic cell; a third code segment configured to calculate a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell; and a fourth code segment configured to determine that the logic cell fails the clock gating check if the clock difference time is negative; wherein said third code segment is further configured to: subtract approximately half of a clock transition period from the clock difference time; and subtract approximately half of a gating signal transition period from the clock difference time.
Claim 13
Dependent Claim
26 words
The program code of claim 9 , wherein said third code segment is further configured to subtract a minimum buffer period from the clock difference time.
Claim 14
Dependent Claim
27 words
The program code of claim 9 , wherein said third code segment is further configured to subtract a maximum overlap time period from the clock difference time.
Claim 15
Dependent Claim
27 words
The program code of claim 9 , wherein said third code segment is further configured to subtract a reserve buffer time period from the clock difference time.
Claim 16
Dependent Claim
127 words
A clock gating check system that performs clock gating check on a logic cell comprising: logic that determines a clock transition time of a clock signal input into the logic cell; logic that determines a transition time of at least one gating signal input into the logic cell; logic that calculates a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell; and logic that determines the logic cell fails the clock gating check if the clock difference time is negative; logic that subtracts approximately half of a clock transition period from the clock difference time; and logic that subtracts approximately half of a gating signal transition period from the clock difference time.
Claim 17
Dependent Claim
127 words
A clock gating check system that performs clock gating check on a logic cell comprising: logic that determines a clock transition time of a clock signal input into the logic cell; logic that determines a transition time of at least one gating signal input into the logic cell; logic that calculates a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell; and logic that determines the logic cell fails the clock gating check if the clock difference time is negative; logic that subtracts approximately half of a clock transition period from the clock difference time; and logic that subtracts approximately half of a gating signal transition period from the clock difference time.
Claim 18
Dependent Claim
23 words
The clock gating check system of claim 13 , further comprising: logic that subtracts a minimum buffer period from the clock difference time.
Claim 19
Dependent Claim
24 words
The clock gating check system of claim 13 , further comprising: logic that subtracts a maximum overlap time period from the clock difference time.
Claim 20
Dependent Claim
24 words
The clock gating check system of claim 13 , further comprising: logic that subtracts a reserve buffer time period from the clock difference time.
Claim 21
Independent Claim
113 words
A method for performing a clock gating check on a logic cell comprising the steps of: providing a timing database comprising clock signal and gating signal timing information, wherein the timing information includes information about a clock transition time of a clock signal to be input into the logic cell and a transition time of at least one gating signal to be input into the logic cell; determining that there is no transition overlap between the clock transition time and the transition time of the at least one gating signal; and determining that the logic cell passes the clock gating check responsive to the step of determining that there is no transition overlap.
Claim 22
Independent Claim
113 words
A method for performing a clock gating check on a logic cell comprising the steps of: providing a timing database comprising clock signal and gating signal timing information, wherein the timing information includes information about a clock transition time of a clock signal to be input into the logic cell and a transition time of at least one gating signal to be input into the logic cell; determining that there is no transition overlap between the clock transition time and the transition time of the at least one gating signal; and determining that the logic cell passes the clock gating check responsive to the step of determining that there is no transition overlap.
Claim 23
Dependent Claim
39 words
The method of claim 17 , wherein the step of determining that there is no transition overlap comprises: calculating a clock difference time between the clock transition time and the transition time of the at least one gating signal.
Claim 24
Independent Claim
161 words
A method for performing a clock gating check on a logic cell comprising the steps of: providing a timing database comprising clock signal and gating signal timing information, wherein the timing information includes information about a clock transition time of a clock signal to be input into the logic cell and a transition time of at least one gating signal to be input into the logic cell; determining that there is no transition overlap between the clock transition time and the transition time of the at least one gating signal; determining that the logic cell passes the clock gating check responsive to the step of determining that there is no transition overlap; calculating a clock difference time between the clock transition time and the transition time of the at least one gating signal; subtracting approximately one-half of a clock transition period from the clock difference time; and subtracting approximately one-half of a gating signal transition period from the clock difference time.
Claim 25
Independent Claim
161 words
A method for performing a clock gating check on a logic cell comprising the steps of: providing a timing database comprising clock signal and gating signal timing information, wherein the timing information includes information about a clock transition time of a clock signal to be input into the logic cell and a transition time of at least one gating signal to be input into the logic cell; determining that there is no transition overlap between the clock transition time and the transition time of the at least one gating signal; determining that the logic cell passes the clock gating check responsive to the step of determining that there is no transition overlap; calculating a clock difference time between the clock transition time and the transition time of the at least one gating signal; subtracting approximately one-half of a clock transition period from the clock difference time; and subtracting approximately one-half of a gating signal transition period from the clock difference time.
Claim 26
Independent Claim
97 words
A system for performing a clock gating check on a logic cell comprising: means for providing a timing database comprising clock signal and gating signal timing information, wherein the timing information includes information about a clock transition time of a clock signal to be input into the logic cell and a transition time of at least one gating signal to be input into the logic cell; and mcans for determining that there is no transition overlap between the clock transition time and the transition time of the at least one gating signal input into the logic cell.
Claim 27
Independent Claim
97 words
A system for performing a clock gating check on a logic cell comprising: means for providing a timing database comprising clock signal and gating signal timing information, wherein the timing information includes information about a clock transition time of a clock signal to be input into the logic cell and a transition time of at least one gating signal to be input into the logic cell; and mcans for determining that there is no transition overlap between the clock transition time and the transition time of the at least one gating signal input into the logic cell.
Claim 28
Dependent Claim
32 words
The system of claim 20 , further comprising: means for determining that the logic cell passes the clock gating check responsive to the step of determining that there is no transition overlap.
Claim 29
Independent Claim
101 words
A system for performing a clock gating check on a logic cell, the system comprising: memory having stored therein a timing database comprising clock signal and gating signal timing information, wherein the timing information includes information about a clock transition time of a clock signal to be input into the logic cell and a transition time of at least one gating signal to be input into the logic cell; and at least one processor that is programmed to determine that there is no transition overlap between the clock transition time and the transition time of the at least one gating signal.
Claim 30
Independent Claim
101 words
A system for performing a clock gating check on a logic cell, the system comprising: memory having stored therein a timing database comprising clock signal and gating signal timing information, wherein the timing information includes information about a clock transition time of a clock signal to be input into the logic cell and a transition time of at least one gating signal to be input into the logic cell; and at least one processor that is programmed to determine that there is no transition overlap between the clock transition time and the transition time of the at least one gating signal.
Claim 31
Dependent Claim
36 words
The system of claim 22 , wherein the at least one processor is programmed to calculate a clock difference time between the clock transition time and the transition time of the at least one gating signal.
Claim 32
Independent Claim
170 words
A system for performing a clock gating check on a logic cell, the system comprising: memory having stored therein a timing database comprising clock signal and gating signal timing information, wherein the timing information includes information about a clock transition time of a clock signal to be input into the logic cell and a transition time of at least one gating signal input to be into the logic cell; and at least one processor that is programmed to determine that there is no transition overlap between the clock transition time and the transition time of the at least one gating signal; wherein the at least one processor is programmed to calculate a clock difference time between the clock transition time and the transition time of the at least one gating signal; and wherein the at least one processor is programmed to subtract approximately one-half of a clock transition period from the clock difference time, and to subtract approximately one-half of a gating signal transition period from the clock difference time.
Claim 33
Independent Claim
170 words
A system for performing a clock gating check on a logic cell, the system comprising: memory having stored therein a timing database comprising clock signal and gating signal timing information, wherein the timing information includes information about a clock transition time of a clock signal to be input into the logic cell and a transition time of at least one gating signal input to be into the logic cell; and at least one processor that is programmed to determine that there is no transition overlap between the clock transition time and the transition time of the at least one gating signal; wherein the at least one processor is programmed to calculate a clock difference time between the clock transition time and the transition time of the at least one gating signal; and wherein the at least one processor is programmed to subtract approximately one-half of a clock transition period from the clock difference time, and to subtract approximately one-half of a gating signal transition period from the clock difference time.
Claim 34
Independent Claim
104 words
A method for performing a clock gating check on a logic cell comprising the steps of: providing a clock transition value of a clock signal to be input into the logic cell and a transition value of at least one gating signal to be input into the logic cell; providing a value indicating a permissible level of overlap between the clock transition value and the transition value of the at least one gating signal; and determining that a transition overlap between the clock transition value and the transition value of the at least one gating signal does not exceed the permissible level of overlap.
Claim 35
Independent Claim
104 words
A method for performing a clock gating check on a logic cell comprising the steps of: providing a clock transition value of a clock signal to be input into the logic cell and a transition value of at least one gating signal to be input into the logic cell; providing a value indicating a permissible level of overlap between the clock transition value and the transition value of the at least one gating signal; and determining that a transition overlap between the clock transition value and the transition value of the at least one gating signal does not exceed the permissible level of overlap.
Claim 36
Dependent Claim
52 words
The method of claim 25 , further comprising: determining that the logic cell passes the clock gating check responsive to the step of determining that the transition overlap between the clock transition value and the transition value of the at least one gating signal does not exceed the permissible level of overlap.
Claim 37
Dependent Claim
28 words
The method of claim 25 , wherein the clock transition value and the transition value of the at least one gating signal are specified in a timing database.
Claim 38
Dependent Claim
26 words
The method of claim 27 , wherein the value indicating a permissible level of overlap is specified in a control file corresponding to the timing database.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-10-19 | 2008-04-19 | 2008-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-10-19 | 2012-04-19 | 2012-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-10-19 | 2016-04-19 | 2016-10-19 | $7700.00 | Window Closed / Lapsed |