Patent EP0823788A2 successfully refreshed from Google Patents.
US5657239A
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Timing verification using synchronizers and timing constraints
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-10-30
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Granted: 1997-08-12
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Expires: 2012-10-30
Abstract
Abstract A computer-based method and program for improving a design of a circuit through analysis of a computer stored model of the circuit. Individual synchronization points are identified in the circuit at each of which a signal may be blocked or allowed to pass in response to appearance of a second signal at the synchronization point. The timing of the circuit is verified based on the individual synchronization points.
Inventors
- 👤 Joel J. Grodstein
- 👤 Nicholas L. Rethman
- 👤 Jeng-Wei Pan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:40
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/3312
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
76 words
A computer-based method for improving a design of a circuit through analysis of a computer stored model of said circuit, said method comprising identifying individual synchronization points independent of timing constraints at said points in said circuit model at each of which a signal may be blocked or allowed to pass in response to appearance of a second signal at said synchronization point and; verifying timing of said circuit based on said identified individual synchronization points.
Claim 2
Dependent Claim
76 words
A computer-based method for improving a design of a circuit through analysis of a computer stored model of said circuit, said method comprising identifying individual synchronization points independent of timing constraints at said points in said circuit model at each of which a signal may be blocked or allowed to pass in response to appearance of a second signal at said synchronization point and; verifying timing of said circuit based on said identified individual synchronization points.
Claim 3
Dependent Claim
41 words
The method of claim 1 further comprising identifying signal paths interconnecting synchronization points in said circuit model, said verifying step comprising determining the timings of hypothetical signals which are propagated along said signal paths and passed by said individual synchronization points.
Claim 4
Dependent Claim
46 words
The method of claim 1 further comprising identifying individual timing constraints in said circuit model each of which represents a required relative time sequence of occurrence of two signals in said circuit model, and verifying timing of said circuit based also on said individual timing constraints.
Claim 5
Dependent Claim
50 words
The method of claim 3 further comprising the steps: receiving at a computer a wirelist representation of said circuit, parsing said wirelist representation to create said model, annotating said model with timing information based on said individual synchronization points, and evaluating said individual timing constraints based on said timing information.
Claim 6
Dependent Claim
22 words
The method of claim 3 wherein at least some of said individual timing constraints are identified by computer analysis of said model.
Claim 7
Dependent Claim
33 words
The method of claim 3 wherein at least one of said individual timing constraints comprises a complete-swing constraint ensuring that a transition on a signal completes early enough to ensure proper circuit function.
Claim 8
Dependent Claim
34 words
The method of claim 3 wherein at least one of said individual timing constraints comprise a glitch-based constraint ensuring that two signals do not overlap to cause a glitch-sensitive node to change its value.
Claim 9
Dependent Claim
27 words
The method of claim 3 wherein at least some of said individual timing constraints require a relative order of transitions of two signals of said circuit model.
Claim 10
Dependent Claim
63 words
The method of claim 1 or 3 wherein said identifying of said individual synchronization points further comprises a subset analysis, wherein said signals comprise sets of transitions, and a first set of transitions is determined to be a proper subset of a second set of transitions, and the circuit model is analyzed with respect to said second set and not said first set.
Claim 11
Dependent Claim
14 words
The method of claim 1 or 3 wherein said model comprises a device-level model.
Claim 12
Dependent Claim
34 words
The method of claim 1 or 3 wherein said identifying of at least some of said individual synchronization points is accomplished independent of any identification of a portion of said circuit as a latch.
Claim 13
Dependent Claim
27 words
The method of claim 1 or 3 wherein said circuit comprises conditional clock signals, and said individual synchronization points are identified relative to said conditional clock signals.
Claim 14
Independent Claim
29 words
The method of claims 1 or 3 wherein said individual synchronization points distinguish by their values said signals that may be blocked or that may be allowed to pass.
Claim 15
Independent Claim
25 words
The method of claims 1 or 3 wherein said individual synchronization points are identified for gate inputs and source inputs of devices of said circuit.
Claim 16
Independent Claim
61 words
The method of claims 1 or 3 wherein said timing constraints are identified under at least one of the following assumptions: analog effects within said circuit can be modelled as worst-case digital effects, said individual synchronization points can be derived based on specified interactions between channel-connected regions of said circuit, and transitivity holds within any single channel-connected region of said circuit.
Claim 17
Independent Claim
40 words
The method of claims 1 or 3 wherein said individual synchronization points are identified based on a minterm description of said circuit, and said minterms are derived by an enumerative evaluation of inputs to a portion of said circuit model.
References Cited (Backward Citations)
US4924430A
Cited
US5095454A
Cited
US5210700A
Cited
US5191541A
Cited
US5278769A
Cited
US5355321A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |