Method and system for shared bus access

Abstract

Abstract An apparatus for controlling access to a PCI bus includes a plurality of USB host controllers, each capable of being connected to a respective USB port. A plurality of PCI cores are each coupled to respective ones of the USB host controllers. A PCI arbiter is coupled to each of the PCI cores. The PCI arbiter is capable of arbitrating multiple requests for the PCI bus, each request initiated by a communication from a respective one of the plurality of USB ports. Full-rate USB data transfer capability is provided between the PCI bus and each of the USB ports. The PCI arbiter receives a plurality of requests for the PCI bus from the PCI cores. A FIFO queue within the PCI arbiter stores a respective record corresponding to each of the PCI cores. A next one of the records is read from the FIFO queue. PCI bus access is granted to the PCI core identified in the next record. The apparatus may include a first plurality of USB ports, each coupled to a respective one of the USB host controllers. A breakout box may be coupled to the first plurality of USB ports. The breakout box is remotely positionable from the first plurality of USB ports. The breakout box includes a second plurality of USB ports, so that full-rate USB data transfer capability is provided between the PCI bus and each one of the second plurality of USB ports.

Inventors

• 👤 Daniel J. Devine
• 👤 James Guziak
• 👤 Kevin J. Lynch

Bibliographic Details