US5375215A
Expired / Lapsed
US
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Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank
Assignee: Renesas Electronics Corp
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Filing: 1991-10-29
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Granted: 1994-12-20
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Expires: 2011-10-29
Abstract
Abstract A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access request need not wait for a previous access request to be finished. Accordingly, the throughput of the system can be improved greatly.
Inventors
- 👤 Makoto Hanawa
- 👤 Tadahiko Nishimukai
- 👤 Osamu Nishii
- 👤 Makoto Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:55
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1642; G06F13/36; G06F15/00; G06F15/16; G06F9/00; G06F9/06
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
421 words
A multiprocessor system comprising: an address bus; a data bus; a plurality of processors each of which is connected to both said address bus and said data bus and each of which sends an access-request address to said address bus, each of the plurality of processors including i) storing means for storing a processor identification number distinct between each of the plurality of processors and ii) first sending means for sending said processor identification number and an access request read/write signal to said data bus when sending said access-request address to said address bus; a plurality of access queues each of which is connected to both said address bus and said data bus, each of the plurality of access queues including a first-in first-out memory each including buffering means for buffering i) a plurality of said access-request addresses, ii) a plurality of said access request read/write signals, iii) a plurality of said processor identification numbers sent from said plurality of processors to said address bus and iv) write data of write access-requests sent from at least one of said plurality of processors to said data bus; a shared memory divided into a plurality of shared memory banks, each of the plurality of shared memory banks respectively corresponding to a one of said plurality of access queues; a plurality of second sending means, each of which being included in the first-in first-out memory of each of plurality of access queues, for sending said plurality of said access-request addresses and said write data of said write access-request from said buffering means to a corresponding one of said plurality of said shared memory banks; a plurality of third sending means, each of which being included in the first-in first-out memory of each of the plurality of access queues, for sending a buffered processor identification number to said data bus when said corresponding one of said plurality of banks of said shared memory sends requested data to said data bus in response to a one of said plurality of said access-request addresses; and, a plurality of comparing means, each of which being included in a one of said plurality of processors, for comparing said buffered processor identification number sent to said data bus from said first-in first-out memory of at least one of said plurality of access queues with said processor identification numbers stored in said storing means and generating an instruction to fetch data on said data bus into a corresponding processor when the comparing of the processor identification numbers detects a coincidence therebetween.
Claim 2
Dependent Claim
421 words
A multiprocessor system comprising: an address bus; a data bus; a plurality of processors each of which is connected to both said address bus and said data bus and each of which sends an access-request address to said address bus, each of the plurality of processors including i) storing means for storing a processor identification number distinct between each of the plurality of processors and ii) first sending means for sending said processor identification number and an access request read/write signal to said data bus when sending said access-request address to said address bus; a plurality of access queues each of which is connected to both said address bus and said data bus, each of the plurality of access queues including a first-in first-out memory each including buffering means for buffering i) a plurality of said access-request addresses, ii) a plurality of said access request read/write signals, iii) a plurality of said processor identification numbers sent from said plurality of processors to said address bus and iv) write data of write access-requests sent from at least one of said plurality of processors to said data bus; a shared memory divided into a plurality of shared memory banks, each of the plurality of shared memory banks respectively corresponding to a one of said plurality of access queues; a plurality of second sending means, each of which being included in the first-in first-out memory of each of plurality of access queues, for sending said plurality of said access-request addresses and said write data of said write access-request from said buffering means to a corresponding one of said plurality of said shared memory banks; a plurality of third sending means, each of which being included in the first-in first-out memory of each of the plurality of access queues, for sending a buffered processor identification number to said data bus when said corresponding one of said plurality of banks of said shared memory sends requested data to said data bus in response to a one of said plurality of said access-request addresses; and, a plurality of comparing means, each of which being included in a one of said plurality of processors, for comparing said buffered processor identification number sent to said data bus from said first-in first-out memory of at least one of said plurality of access queues with said processor identification numbers stored in said storing means and generating an instruction to fetch data on said data bus into a corresponding processor when the comparing of the processor identification numbers detects a coincidence therebetween.
Claim 3
Dependent Claim
61 words
The multiprocessor system according to claim 1, wherein said system further comprises a first arbiter which is connected to said address bus for deciding address bus ownership in response to the request on said address bus, and a second arbiter which is connected to said data bus for deciding data bus ownership in response to the request on said data bus.
Claim 4
Dependent Claim
15 words
The multiprocessor system according to claim 1, wherein said shared memory is a cache memory.
Claim 5
Dependent Claim
30 words
The multiprocessor system according to claim 3, wherein said address bus, said data bus, said plurality of access queues and said cache memory are formed on a single semiconductor substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-19 | 1998-06-20 | 1998-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-19 | 2002-06-20 | 2002-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-19 | 2006-06-20 | 2006-12-20 | $7700.00 | Window Closed / Lapsed |